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參數(shù)資料
| 型號： | WV3HG64M64EEU806D6SG |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 64M X 64 DDR DRAM MODULE, DMA240 |
| 封裝： | ROHS COMPLIANT, DIMM-240 |
| 文件頁數(shù)： | 10/11頁 |
| 文件大?。?/td> | 204K |
| 代理商： | WV3HG64M64EEU806D6SG |
WV3HG64M64EEU-D6
October 2006
Rev. 1
ADVANCED
8
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
DDR2 SDRAM COMPONENT AC TIMING PARAMETERS & SPECIFICATION (cont'd)
0°C ≤ TCASE < +85°C; VCCQ = + 1.8V ± 0.1V, VCC = +1.8V ± 0.1V
AC CHARACTERISTICS
806
665
534
403
PARAMETER
SYMBOL MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
Command
and
Address
Address and control input setup time
tIS
TBD
250
ps
Address and control input hold time
tIH
TBD
375
475
ps
CAS# to CAS# command delay
tCCD
TBD
22
tCK
ACTIVE to ACTIVE (same bank) command
tRC
TBD
55
ns
ACTIVE bank a to ACTIVE bank b command
tRRD
TBD
7.5
ns
ACTIVE to READ or WRITE delay
tRCD
TBD
15
ns
Four Bank Activate period
tFAW
TBD
37.5
ACTIVE to PRECHARGE command
tRAS
TBD
45
70,000
45
70,000
ns
Internal READ to precharge command delay
tRTP
TBD
7.5
ns
Write recovery time
tWR
TBD
15
ns
Auto precharge write recovery + precharge time
tDAL
TBD
tWR + tRP
ns
Internal WRITE to READ command delay
tWTR
TBD
7.5
10
ns
PRECHARGE command period
tRP
TBD
15
PRECHARGE ALL command period
tRPA
TBD
tWR + tCK
ns
LOAD MODE command cycle time
tMRD
TBD
22
tCK
CKE low to CK,CK# uncertainty
tDELAY
TBD
tIS + tCK + tIH
ns
Refresh
REFRESH to REFRESH command interval
tRFC
TBD
127.5
70,000
127.5
70,000
ns
Average periodic refresh interval
tREFI
TBD
7.8
μs
Self
Refresh
Exit self refresh to non-READ command
tXSNR
TBD
tRFC (MIN)
+ 10
tRFC (MIN)
+ 10
ns
Exit self refresh to READ command
tXSRD
TBD
200
tCK
Exit self refresh timing reference
tISXR
TBD
tIS
ps
ODT
ODT turn-on delay
tAOND
TBD
2222
tCK
ODT turn-on
tAON
TBD
tAC (MIN) tAC (MAX)
+ 1000
tAC (MIN) tAC (MAX)
+ 1000
ps
ODT turn-off delay
tAOFD
TBD
2.5
tCK
ODT turn-off
tAOF
TBD
tAC (MIN) tAC (MAX)
+ 600
tAC (MIN) tAC (MAX)
+ 600
ps
ODT turn-on (power-down mode)
tAONPD
TBD
tAC (MIN) +
2000
2 x tCK +
tAC (MAX)
+ 1000
tAC (MIN) +
2000
2 x tCK +
tAC (MAX)
+ 1000
ps
ODT turn-off (power-down mode)
tAOFPD
TBD
tAC (MIN) +
2000
2.5 x tCK +
tAC (MAX)
+ 1000
tAC (MIN) +
2000
2.5 x tCK +
tAC (MAX)
+ 1000
ps
ODT to power-down entry latency
tANPD
TBD
33
tCK
ODT power-down exit latency
tAXPD
TBD
88
tCK
Power-Down
Exit active power-down to READ command,
MR[bit12=0]
tXARD
TBD
22
tCK
Exit active power-down to READ command,
MR[bit12=1]
tXARDS
TBD
6 - AL
tCK
A Exit precharge power-down to any non-READ
command.
tXP
TBD
22
tCK
CKE minimum high/low time
tCKE
TBD
33
tCK
NOTE:
AC specication is based on
SAMSUNG components. Other DRAM manufactures specication may be different.
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