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參數(shù)資料
| 型號： | WV3HG64M64EEU403D4SG |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 64M X 64 DDR DRAM MODULE, 0.6 ns, ZMA200 |
| 封裝： | ROHS COMPLIANT, SODIMM-200 |
| 文件頁數(shù)： | 9/11頁 |
| 文件大?。?/td> | 185K |
| 代理商： | WV3HG64M64EEU403D4SG |
WV3HG64M64EEU-D4
October 2006
Rev. 3
ADVANCED
7
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
DDR2 SDRAM COMPONENT AC TIMING PARAMETERS & SPECIFICATIONS
AC CHARACTERISTICS
665
534
403
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
Clock cycle time
CL = 5
tCK (5)
3,000
8,000
ps
CL = 4
tCK (4)
3,750
8,000
3,750
8,000
5,000
8,000
ps
CL = 3
tCK (3)
5,000
8,000
5,000
8,000
5,000
8,000
ps
CK high-level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
CK low-level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
tCK
Half clock period
tHP
MIN (tCH,
tCL)
MIN (tCH,
tCL)
MIN (tCH,
tCL)
ps
Clock jitter
tJIT
250
ps
Data
DQ output access time from CK/CK#
tAC
-450
+450
-500
+500
-600
+600
ps
Data-out high-impedance window from CK/CK#
tHZ
tAC MAX
ps
Data-out low-impedance window from CK/CK#
tLZ
tAC MIN
tAC MAX
tAC MIN
tAC MAX
tAC MIN
tAC MAX
ps
DQ and DM input setup time relative to DQS
tDS
100
150
ps
DQ and DM input hold time relative to DQS
tDH
225
275
ps
DQ and DM input pulse width (for each input)
tDIPW
0.35
tCK
Data hold skew factor
tQHS
340
400
450
ps
DQ…DQS hold, DQS to rst DQ to go nonvalid, per
access
tQH
tHP - tQHS
ps
Data valid output window (DVW)
tDVW
tQH - tDQSQ
ns
Data
Strobe
DQS input high pulse width
tDQSH
0.35
tCK
DQS input low pulse width
tDQSL
0.35
tCK
DQS output access time from CK/CK#
tDQSCK
-400
+400
-450
+450
-500
+500
ps
DQS falling edge to CK rising … setup time
tDSS
0.2
tCK
DQS falling edge from CK rising … hold time
tDSH
0.2
tCK
DQS…DQ skew, DQS to last DQ valid, per group,
per access
tDQSQ
240
300
350
ps
DQS read preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
tCK
DQS read postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
DQS write preamble setup time
tWPRES
000
p s
DQS write preamble
tWPRE
0.35
tCK
DQS write postamble
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
Write command to rst DQS latching transition
tDQSS
WL
- 0.25
WL +
0.25
WL
- 0.25
WL +
0.25
WL
- 0.25
WL +
0.25
tCK
Address and control input pulse width for each input
tIPW
0.6
tCK
Address and control input setup time
tIS
200
250
350
ps
Address and control input hold time
tIH
275
375
475
ps
Address and control input hold time
tCCD
222
tCK
Note:
AC specication is based on
SAMSUNG components. Other DRAM manufactures specication may be different.
Continued on next page
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WV3HG64M64EEU403D6GG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 64Mx64 DDR2 SDRAM UNBUFFERED |
| WV3HG64M64EEU403D6MG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 64Mx64 DDR2 SDRAM UNBUFFERED |
| WV3HG64M64EEU403D6SG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 64Mx64 DDR2 SDRAM UNBUFFERED |
| WV3HG64M64EEU534D4IMG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 64Mx64 DDR2 SDRAM UNBUFFERED, SO-DIMM |
| WV3HG64M64EEU534D4ISG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 64Mx64 DDR2 SDRAM UNBUFFERED, SO-DIMM |
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