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White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
WV3EG6434S-BD4
April 2005
Rev. 0
ADVANCED
White Electronic Designs Corp. reserves the right to change products or specications without notice.
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC
OPERATING CONDITIONS (Continued)
0°C ≤ TA ≤ 70°C, VCC = +2.5V ±0.2V, VCCQ = +2.5V ±0.2V
Parameter
Symbol
335
262
265
Unit
Note
Min
Max
Min
Max
Min
Max
Mode register set cycle time
tMRD
12
15
ns
DQ & DM setup time to DQS
tDS
0.45
0.5
ns
7
DQ & DM hold time to DQS
tDH
0.45
0.5
ns
7
Control & Address input pulse width
tIPW
2.2
ns
DQ & DM input pulse width
tDIPW
1.75
ns
Power down exit time
tPDEX
6
7.5
ns
Exit self refresh to non-Read command
tXSNR
75
ns
4
Exit self refresh to read command
tXSRD
200
tCK
Refresh interval time
tREFI
7.8
us
1
Output DQS valid window
tQH
tHP-tQHS
—tHP-tQHS
—ns
5
Clock half period
tHP
tCLmin or
tCHmin
—
tCLmin or
tCHmin
—
tCLmin or
tCHmin
—ns
Data hold skew factor
tQHS
0.55
0.75
ns
DQS write postamble time
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
3
Active to Read with Auto precharge command
tRAP
18
20
Autoprecharge write recovery + Precharge
time
tDAL
(tWR/tCK) +
(tRP/tCK)
(tWR/tCK) +
(tRP/tCK)
(tWR/tCK) +
(tRP/tCK)
tCK
1.
Maximum burst refresh cycle : 8
2.
The specic requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from High_Z to logic Low) applies when no writes were
previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS.
3.
The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter, but system performance (bus turnaround) will degrade
accordingly.
4.
A write command can be applied with tRCD satised after this command.
5.
For registered DIMMs, tCL and tCH are >_ 45% of the period including both the half period jitter (tJIT(HP)) of the PLL and the half period jitter due to crosstalk (tJIT(crosstalk)) on
the DIMM.
6.
Input Setup/Hold Slew Rate Derating
Input Setup/Hold Slew Rate
tIS
tIH
(V/ns)
(ps)
0.5
0
0.4
+50
0.3
+100
This derating table is used to increase tIS/tIH in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate based on the lesser of AC-AC slew rate
and DC-DC slew rate.
7.
I/O Setup/Hold Slew Rate Derating
I/O Setup/Hold Slew Rate
tDS
tDH
(V/ns)
(ps)
0.5
0
0.4
+75
0.3
+150
This derating table is used to increase tDS/tDH in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate based on the lesser of AC-AC slew rate
and DC-DC slew rate.