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參數(shù)資料
| 型號： | WV3EG264M72ESFR265D4-M |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 128M X 72 DDR DRAM MODULE, 0.75 ns, DMA200 |
| 封裝： | SO-DIMM-200 |
| 文件頁數(shù)： | 10/11頁 |
| 文件大?。?/td> | 181K |
| 代理商： | WV3EG264M72ESFR265D4-M |
WV3EG264M72ESFR-D4
August 2005
Rev. 0
ADVANCED
8
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
SERIAL PRESENT DETECT INFORMATION (cont'd)
Byte #
Function described
Function Supported
Hex value
265
262
335
265
262
335
13
Primary DDR SDRAM width
x8
08h
14
Error checking DDR SDRAM data width
x8
08h
15
Minimum clock delay for back-to-back random column address
tCCD = 1CLK
01h
16
DDR SDRAM device attributes: Burst lengths supported
2,4,8
0Eh
17
DDR SDRAM device attributes: # of banks on each DDR SDRAM
4 banks
04h
18
DDR SDRAM device attributes: CAS Latency supported
2,2.5
0Ch
19
DDR SDRAM device attributes: CS Latency
0CLK
01h
20
DDR SDRAM device attributes: WE Latency
1CLK
02h
21
DDR SDRAM module attributes
Registered address & control inputs
and On-card DLL
26h
22
DDR SDRAM device attributes: General
+/-0.2V voltage tolerance
C0h
23
DDR SDRAM cycle time at CL =2
10ns
7.5ns
A0h
75h
24
DDR SDRAM Access time from clock at CL =2
±0.75
±0.7
75h
70h
25
DDR SDRAM cycle time at CL =1.5
—
00h
26
DDR SDRAM Access time from clock at CL =1.5
—
00h
27
Minimum row precharge time (=tRP)
20ns
18ns
50h
48h
28
Minimum row activate to row active delay (=tRRD)
15ns
12ns
3Ch
30h
29
Minimum RAS to CAS delay (=tRCD)
20ns
18ns
50h
48h
30
Minimum active to precharge time (=tRAS)
45ns
42ns
2Dh
2Ah
31
Module ROW density
512MB
80h
32
Command and address signal input setup time
0.9ns
0.8ns
A0h
80h
33
Command and address signal input hold time
0.9ns
0.8ns
A0h
80h
34
Data signal input setup time
0.5ns
0.45ns
50h
45h
35
Data signal input hold time
0.5ns
0.45ns
50h
45h
36-40
Superset information (may be used in future)
—
00h
41
DDR SDRAM Minimum Active to Active/Auto Refresh Time (tRC)
65ns
60ns
41h
3Ch
42
DDR SDRAM Minimim Auto-Refresh to Active/Auto-Refresh
Commmand Period (tRFC)
75ns
72ns
4Bh
48h
43
DDR SDRAM Maximum Device Cycle Time (tCK max)
13ns
12ns
34h
30h
44
DDR SDRAM DQS-DQ Skew for DQS and associated DQ signals
(tDQSQmax)
0.50ns
0.45ns
50h
45h
45
DDR SDRAM Read Data Hold Skew Factor (tQHS)
0.75ns
0.50ns
75h
50h
46
Reserved
00
00h
47
DIMM Height
Standard/Low prole
01h
48-61
Superset information (may be used in future)
—
00h
62
SPD data revision code
Initial release
10h
63
Checksum for Bytes 0 ~ 62
—
69h
39h
6Fh
64 - 127
Manufacturer INFO
—
00h
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PDF描述 |
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| WV3EG264M72ESFR265D4-S | 128M X 72 DDR DRAM MODULE, 0.75 ns, DMA200 |
| W1D128M72R8A-5AL-FA1 | 128M X 8 DDR DRAM MODULE, 0.5 ns, DMA240 |
| W1D128M72R8A-5AL-FA2 | 128M X 8 DDR DRAM MODULE, 0.5 ns, DMA240 |
| W1D128M72R8A-5AP-FA1 | 128M X 8 DDR DRAM MODULE, 0.5 ns, DMA240 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WV3EG264M72ESFR265D4-MG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM REGISTERED, w/PLL |
| WV3EG264M72ESFR265D4-SG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM REGISTERED, w/PLL |
| WV3EG264M72ESFR335D4-MG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM REGISTERED, w/PLL |
| WV3EG264M72ESFR335D4-SG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM REGISTERED, w/PLL |
| WV3EG264M72ESFR-D4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM REGISTERED, w/PLL |
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