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參數(shù)資料
| 型號： | WV3EG128M72EFSR335D3MG |
| 英文描述： | 1GB - 128Mx72 DDR SDRAM REGISTERED w/PLL, FBGA |
| 中文描述： | 1GB的- 128Mx72 DDR SDRAM的注冊瓦特/鎖相環(huán)，F(xiàn)BGA封裝 |
| 文件頁數(shù)： | 4/13頁 |
| 文件大?。?/td> | 334K |
| 代理商： | WV3EG128M72EFSR335D3MG |
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
March 2005
Rev. 0
ADVANCED
WV3EG128M72EFSR-D3
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to V
SS
Voltage on V
CC
supply relative to V
SS
Storage Temperature
Power Dissipation
Short Circuit Current
Note:
Permanent device damage may occur if ‘ABSOLUTE MAXIMUM RATINGS’ are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability
Symbol
V
IN
, V
OUT
V
CC
, V
CCQ
T
STG
P
D
I
OS
Value
-0.5 to 3.6
-1.0 to 3.6
-55 to +150
18
50
Units
V
V
°C
W
mA
DC CHARACTERISTICS
0°C
≤
T
A
≤
70°C, V
CC
= 2.5V ± 0.2V
Parameter
Supply Voltage (for device with nominal V
CC
of 2.5V)
I/O Supply Voltage
I/O Reference Voltage
I/O Termination Voltage (systems)
Input Logic High Voltage
Input Logic Low Voltage
Input Voltage Level, CK and CK# inputs
Input Differential Voltage, CK and CK# inputs
Input Crossing Point Voltage, CK and CK# inputs
Input Leakage Current
Output Leakage Current
Output High Current (Normal strength driver); V
OUT
= V
TT
+ 0.84V
Output High Current (Normal strength driver); V
OUT
= V
TT
- 0.84V
Output High Current (Half strength driver); V
OUT
= V
TT
+ 0.45V
Output High Current (Half strength driver); V
OUT
= V
TT
- 0.45V
Notes:
1.
Includes ± 25mV margin for DC offset on V
REF
, and a combined total of ± 50mV
margin for all AC noise and DC offset on V
REF
, bandwidth limited to 20MHz. The
DRAM must accommodate DRAM current spikes on V
REF
and internal DRAM
noise coupled TO V
REF
, both of which may result in V
REF
noise. V
REF
should be
de-coupled with an inductance of ≤ 3nH.
2.
V
TT
is not applied directly to the device. V
TT
is a system supply for signal
termination resistors, is expected to be set equal to V
REF
, and must track variations
in the DC level of V
REF
3.
V
ID
is the magnitude of the difference between the input level on CK and the input
level on CK#.
Symbol
V
CC
V
CCQ
V
REF
V
TT
V
IH
(DC)
V
IL
(DC)
V
IN
(DC)
V
ID
(DC)
V
IX
(DC)
I
L
I
OZ
I
OH
I
OL
I
OH
I
OL
Min
2.3
2.3
Max
2.3
2.3
Unit
V
V
V
V
V
V
V
V
V
uA
uA
mA
mA
mA
mA
V
CCQ
/2-50mV
V
REF
-0.04
V
REF
+0.15
-0.3
-0.3
0.3
1.15
-2
-5
-16.8
16.8
-9
9
V
CCQ
/2+50mV
V
REF
+0.04
V
CCQ
+0.3
V
REF
-0.15
V
CCQ
+0.3
V
CCQ
+0.6
1.35
2
5
CAPACITANCE
T
A
= 25°C. f = 1MHz, V
CC
= 2.5V
Parameter
Input Capacitance (A0-A12)
Input Capacitance (RAS#, CAS#, WE#)
Input Capacitance (CKE0, CKE1)
Input Capacitance (CK0#, CK0)
Input Capacitance (CS0#, CS1#)
Input Capacitance (DQM0-DQM8)
Input Capacitance (BA0-BA1)
Data input/output capacitance (DQ0-DQ63)(DQS)
Data input/output capacitance (CB0-CB7)
Symbol
C
IN1
C
IN2
C
IN3
C
IN4
C
IN5
C
IN6
C
IN7
C
OUT
C
OUT
Max
11
11
11
12
11
15
11
15
15
Unit
pF
pF
pF
pF
pF
pF
pF
pF
pF
4.
These parameters should be tested at the pin on actual components and may
be checked at either the pin or the pad in simulation. The AC and DC input
specifications are relative to a V
REF
envelop that has been bandwidth limited to
200MHZ.
The value of V
IX
is expected to equal 0.5*V
CCQ
of the transmitting device and must
track variations in the dc level of the same.
These charactericteristics obey the SSTL-2 class II standards.
5.
6.
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| WV3EG128M72EFSR335D3SF | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx72 DDR SDRAM REGISTERED w/PLL, FBGA |
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| WV3EG128M72EFSR-D3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx72 DDR SDRAM REGISTERED w/PLL, FBGA |
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| WV3EG216M64STSU335D4NG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:256MB - 2x16Mx64 DDR SDRAM UNBUFFERED |
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