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參數資料
| 型號： | WV3EG128M72EFSR265D3SF |
| 英文描述： | 1GB - 128Mx72 DDR SDRAM REGISTERED w/PLL, FBGA |
| 中文描述： | 1GB的- 128Mx72 DDR SDRAM的注冊瓦特/鎖相環(huán)，FBGA封裝 |
| 文件頁數： | 6/13頁 |
| 文件大?。?/td> | 334K |
| 代理商： | WV3EG128M72EFSR265D3SF |
6
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
March 2005
Rev. 0
ADVANCED
WV3EG128M72EFSR-D3
I
DD
SPECIFICATIONS AND TEST CONDITIONS
Recommended operating conditions, 0°C
≤
T
A
≤
70°C, V
CCQ
= 2.5V ± 0.2V, V
CC
= 2.5V ± 0.2V
Includes PLL and register power
Parameter
Operating Current
Symbol
I
DD0
Conditions
One device bank; Active - Precharge; t
=t
(MIN);
t
=t
(MIN); DQ,DM and DQS inputs changing once
per clock cycle; Address and control inputs changing
once every two cycles.
One device bank; Active-Read-Precharge Burst = 2;
t
=t
(MIN); t
=t
(MIN); l
= 0mA; Address and
control inputs changing once per clock cycle.
All device banks idle; Power-down mode; t
CK
=t
CK
(MIN);
CKE=(low)
CS# = High; All device banks idle; t
=t
(MIN); CKE
= high; Address and other control inputs changing once
per clock cycle. V
IN
= V
REF
for DQ, DQS and DM.
One device bank active; Power-Down mode; t
CK
(MIN);
CKE=(low)
CS# = High; CKE = High; One device bank; Active-
Precharge; t
=t
(MAX); t
=t
(MIN); DQ, DM and
DQS inputs changing twice per clock cycle; Address
and other control inputs changing once per clock cycle.
Burst = 2; Reads; Continuous burst; One device bank
active; Address and control inputs changing once per
clock cycle; T
CK
= T
CK
(MIN); l
OUT
= 0mA.
Burst = 2; Writes; Continuous burst; One device bank
active; Address and control inputs changing once per
clock cycle; t
=t
(MIN); DQ,DM and DQS inputs
changing once per clock cycle.
t
RC
= t
RC
(MIN)
CKE
≤
0.2V
Four bank interleaving Reads (BL=4) with auto
precharge with t
=t
(MIN); t
=t
(MIN); Address
and control inputs change only during Active Read or
Write commands.
DDR333@
CL=2.5
Max
4725
DDR266@
CL=2
Max
4725
DDR266@
CL=2.5
Max
4725
Units
mA
Operating Current
I
DD1
5265
5265
5265
mA
Precharge Power-
Down Standby Current
Idle Standby Current
I
DD2P
180
180
180
rnA
I
DD2F
1930
1930
1930
mA
Active Power-Down
Standby Current
Active Standby Current
I
DD3P
1260
1260
1260
mA
I
DD3N
2110
2110
2110
mA
Operating Current
I
DD4R
5355
5355
5355
mA
Operating Current
I
DD4W
5535
5175
5175
rnA
Auto Refresh Current
Self Refresh Current
Operating Current
I
DD5
I
DD6
I
DD7A
7640
455
9675
7605
455
9585
7605
455
9585
mA
mA
mA
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相關代理商/技術參數 |
參數描述 |
|---|---|
| WV3EG128M72EFSR265D3SG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx72 DDR SDRAM REGISTERED w/PLL, FBGA |
| WV3EG128M72EFSR335D3MF | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx72 DDR SDRAM REGISTERED w/PLL, FBGA |
| WV3EG128M72EFSR335D3MG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx72 DDR SDRAM REGISTERED w/PLL, FBGA |
| WV3EG128M72EFSR335D3SF | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx72 DDR SDRAM REGISTERED w/PLL, FBGA |
| WV3EG128M72EFSR335D3SG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx72 DDR SDRAM REGISTERED w/PLL, FBGA |
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