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參數(shù)資料
| 型號(hào)： | WV3EG128M72EFSR262D3MG |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 128M X 72 DDR DRAM MODULE, 0.75 ns, DMA184 |
| 封裝： | ROHS COMPLIANT, DIMM-184 |
| 文件頁(yè)數(shù)： | 10/13頁(yè) |
| 文件大小： | 382K |
| 代理商： | WV3EG128M72EFSR262D3MG |
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6
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
March 2005
Rev. 0
ADVANCED
WV3EG128M72EFSR-D3
IDD SPECIFICATIONS AND TEST CONDITIONS
Recommended operating conditions, 0°C TA 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V
Includes PLL and register power
Parameter
Symbol
Conditions
DDR333@
CL=2.5
Max
DDR266@
CL=2
Max
DDR266@
CL=2.5
Max
Units
Operating Current
IDD0
One device bank; Active - Precharge; tRC=tRC (MIN);
tCK=tCK (MIN); DQ,DM and DQS inputs changing once
per clock cycle; Address and control inputs changing
once every two cycles.
4725
mA
Operating Current
IDD1
One device bank; Active-Read-Precharge Burst = 2;
tRC=tRC (MIN); tCK=tCK (MIN); lOUT = 0mA; Address and
control inputs changing once per clock cycle.
5265
mA
Precharge Power-
Down Standby Current
IDD2P
All device banks idle; Power-down mode; tCK=tCK (MIN);
CKE=(low)
180
rnA
Idle Standby Current
IDD2F
CS# = High; All device banks idle; tCK=tCK (MIN); CKE
= high; Address and other control inputs changing once
per clock cycle. VIN = VREF for DQ, DQS and DM.
1930
mA
Active Power-Down
Standby Current
IDD3P
One device bank active; Power-Down mode; tCK (MIN);
CKE=(low)
1260
mA
Active Standby Current
IDD3N
CS# = High; CKE = High; One device bank; Active-
Precharge; tRC=tRAS (MAX); tCK=tCK (MIN); DQ, DM and
DQS inputs changing twice per clock cycle; Address
and other control inputs changing once per clock cycle.
2110
mA
Operating Current
IDD4R
Burst = 2; Reads; Continuous burst; One device bank
active; Address and control inputs changing once per
clock cycle; TCK= TCK (MIN); lOUT = 0mA.
5355
mA
Operating Current
IDD4W
Burst = 2; Writes; Continuous burst; One device bank
active; Address and control inputs changing once per
clock cycle; tCK=tCK (MIN); DQ,DM and DQS inputs
changing once per clock cycle.
5535
5175
rnA
Auto Refresh Current
IDD5
tRC = tRC (MIN)
7640
7605
mA
Self Refresh Current
IDD6
CKE 0.2V
455
mA
Operating Current
IDD7A
Four bank interleaving Reads (BL=4) with auto
precharge with tRC=tRC (MIN); tCK=tCK (MIN); Address
and control inputs change only during Active Read or
Write commands.
9675
9585
mA
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WV3EG128M72EFSR262D3SF | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx72 DDR SDRAM REGISTERED w/PLL, FBGA |
| WV3EG128M72EFSR262D3SG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx72 DDR SDRAM REGISTERED w/PLL, FBGA |
| WV3EG128M72EFSR265D3MF | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx72 DDR SDRAM REGISTERED w/PLL, FBGA |
| WV3EG128M72EFSR265D3MG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx72 DDR SDRAM REGISTERED w/PLL, FBGA |
| WV3EG128M72EFSR265D3SF | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx72 DDR SDRAM REGISTERED w/PLL, FBGA |
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