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參數(shù)資料
| 型號(hào)： | WV3DG7266V75D1 |
| 英文描述： | 512MB -2x32Mx72 SDRAM, UNBUFFERED, w/PLL |
| 中文描述： | 512MB的- 2x32Mx72內(nèi)存，無緩沖，瓦特/鎖相環(huán) |
| 文件頁數(shù)： | 5/8頁 |
| 文件大小： | 182K |
| 代理商： | WV3DG7266V75D1 |
WV3DG7266V-D1
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
August 2005
Rev. 1
PRELIMINARY
OPERATING AC PARAMETER
Symbol
Parameter
Version
75
15
20
20
45
100
65
2
2 CLK + tRP
1
1
1
2
1
Unit
Note
7
15
15
15
45
10
20
20
20
50
Row active to row active delay
RAS# to CAS# delay
Row precharge time
Row active time
t
RRD(min)
t
RCD(min)
t
RP(min)
t
RAS(min)
t
RAS(max)
t
RC(min)
t
RDL(min)
t
DAL(min)
t
CDL(min)
t
BDL(min)
t
CCD(min)
ns
ns
ns
ns
us
ns
CLK
—
CLK
CLK
CLK
ea
1
1
1
1
Row cycle time
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
Col. address to col. address delay
Number of valid output data
60
70
1
2
2
2
3
4
CAS latency=3
CAS latency=2
Notes:
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
AC OPERATING TEST CONDITIONS
V
CC
= 3.3v, 0°C - 70°C
Parameter
AC input levels (V
IH
/V
IL
)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
2.4/0.4
1.4
t
R
/t
F
= 1/1
1.4
See Fig. 2
Unit
V
V
ns
V
DC OUTPUT LOAD CIRCUIT
AC OUTPUT LOAD CIRCUIT
3.3V
1200
870
Output
50pF
V
OH
(DC) = 2.4V, I
OH
= -2mA
V
OL
(DC) = 0.4V, I
OL
= 2mA
Vtt = 1.4V
50
Output
50pF
Z0 = 50
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WV3DG7266V7D1 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB -2x32Mx72 SDRAM, UNBUFFERED, w/PLL |
| WV3DG7266V-D1 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB -2x32Mx72 SDRAM, UNBUFFERED, w/PLL |
| WV3EG128M72EFSR262D3MF | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx72 DDR SDRAM REGISTERED w/PLL, FBGA |
| WV3EG128M72EFSR262D3MG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx72 DDR SDRAM REGISTERED w/PLL, FBGA |
| WV3EG128M72EFSR262D3SF | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx72 DDR SDRAM REGISTERED w/PLL, FBGA |
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