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參數(shù)資料
| 型號： | WS512K32-35G4TI |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | SRAM |
| 英文描述： | 512K X 32 MULTI DEVICE SRAM MODULE, 35 ns, CQFP68 |
| 封裝： | 40 X 40 MM, 3.50 MM HEIGHT, HERMETIC SEALED, CERAMIC, QFP-68 |
| 文件頁數(shù)： | 6/11頁 |
| 文件大?。?/td> | 577K |
| 代理商： | WS512K32-35G4TI |
4
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
WS512K32-XXX
May 2006
Rev. 17
AC CHARACTERISTICS
VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
FIGURE. 4 – AC TEST CIRCUIT
VZ ≈ 1.5V
(Bipolar Supply)
IOL
Current Source
D.U.T.
Ceff = 50 pf
Current Source
IOH
AC Test Conditions
Parameter
Typ
Unit
Input Pulse Levels
VIL = 0, VIH = 3.0
V
Input Rise and Fall
5
ns
Input and Output Reference Level
1.5
V
Output Timing Reference Level
1.5
V
Notes:
VZ is programmable from -2V to +7V.
IOL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75 .
VZ is typically the midpoint of VOH and VOL.
IOL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
Parameter
Write Cycle
Symbol
-15
-17
-20
-25
-35
-45
-55
Units
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Write Cycle Time
tWC
15
17
20
25
35
45
55
ns
Chip Select to End of Write
tCW
13
15
17
25
35
50
ns
Address Valid to End of Write
tAW
13
15
17
25
35
50
ns
Data Valid to End of Write
tDW
10
11
12
13
20
25
ns
Write Pulse Width
tWP
13
15
17
25
35
40
ns
Address Setup Time
tAS
2222222
ns
Address Hold Time
tAH
0000055
ns
Output Active from End of Write
tOW1
2234455
ns
Write Enable to Output in High Z
tWHZ1
8
9
11
13
15
20
ns
Data Hold Time
tDH
0000000
ns
Parameter
Read Cycle
Symbol
-15
-17
-20
-25
-35
-45
-55
Units
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Read Cycle Time
tRC
15
17
20
25
35
45
55
ns
Address Access Time
tAA
15
17
20
25
35
45
55
ns
Output Hold from Address Change
tOH
0000000
ns
Chip Select Access Time
tACS
15
17
20
25
35
45
55
ns
Output Enable to Output Valid
tOE
8
9
10
12
25
ns
Chip Select to Output in Low Z
tCLZ1
2222444
ns
Output Enable to Output in Low Z
tOLZ1
0000000
ns
Chip Disable to Output in High Z
tCHZ1
12
15
20
ns
Output Disable to Output in High Z
tOHZ1
12
15
20
ns
1. This parameter is guaranteed by design but not tested.
2. The Address Setup Time of minimum 2ns is for the G2U, G1U and H1 packages. tAS minimum for the G4T package is 0ns.
AC CHARACTERISTICS
VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
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相關代理商/技術參數(shù) |
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|---|---|
| WS512K32-35G4TIA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SRAM|512KX32|CMOS|QFL|68PIN|CERAMIC |
| WS512K32-35G4TM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x32 SRAM Module |
| WS512K32-35G4TMA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SRAM|512KX32|CMOS|QFL|68PIN|CERAMIC |
| WS512K32-35G4TQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x32 SRAM Module |
| WS512K32-35G4TQA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SRAM|512KX32|CMOS|QFL|68PIN|CERAMIC |
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