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參數(shù)資料
| 型號： | WS1M8V-85CIA |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | SRAM |
| 英文描述： | 1M X 8 STANDARD SRAM, 85 ns, CDIP32 |
| 封裝： | 0.600 INCH, SINGLE CAVITY, HERMETIC SEALED, SIDE BRAZED, CERAMIC, DIP-32 |
| 文件頁數(shù)： | 1/5頁 |
| 文件大?。?/td> | 138K |
| 代理商： | WS1M8V-85CIA |
1
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WS1M8V-XCX
2x512Kx8 DUALITHIC SRAM ADVANCED*
FEATURES
s Access Times 70, 85, 100ns
s Evolutionary, Corner Power/Ground Pinout
s Packaging:
32 pin, Hermetic Ceramic DIP (Package 300)
s Organized as two banks of 512Kx8
s Commercial, Industrial and Military Temperature Ranges
s 3.3V Power Supply
s Low Power CMOS
s TTL Compatible Inputs and Outputs
s Output Enable Internally tied to GND.
* This data sheet describes a product that may or may not be under
development and is subject to change or cancellation without notice.
February 2000 Rev. 2
NOTE:
1. CS1 and CS2 are used to select the lower and upper 512Kx8 of the
device. CS1 and CS2 must not be enabled at the same time.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
VCC
A15
A17
WE
A13
A8
A9
A11
CS2
A10
CS1
I/O7
I/O6
I/O5
I/O4
I/O3
PIN CONFIGURATION FOR WS1M8V-XCX
32 DIP
TOP VIEW
BLOCK DIAGRAM
512K x 8
A 0-18
WE
CS 1
CS 2
I/O 0-7
(1)
A0-18
Address Inputs
I/O0-7
Data Input/Output
CS1-2
Chip Selects
WE
Write Enable
VCC
+3.3V Power Supply
GND
Ground
PIN DESCRIPTION
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| WS1M8V-XCX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2X512KX8 Dualithic SRAM Advanced |
| WS1M8-XCX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2X512X8 Dualithic SRAM Preliminary |
| WS1M8-XDJX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SRAM MCP |
| WS1M8-XFX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SRAM MCP |
| WS1M8-XXX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2 x 512K x 8 Dualithic SRAM |
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