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參數(shù)資料
| 型號： | WS1M8V-55CX |
| 英文描述： | 2x512Kx8 Dualithic SRAM(3.3V,2x512Kx8 Dualithic 靜態(tài)RAM（存取時間55ns）) |
| 中文描述： | 2x512Kx8 Dualithic SRAM的電壓（3.3V，2x512Kx8 Dualithic靜態(tài)隨機存儲器（存取時間55ns）） |
| 文件頁數(shù)： | 1/5頁 |
| 文件大?。?/td> | 133K |
| 代理商： | WS1M8V-55CX |
1
White Microelectronics Phoenix, AZ (602) 437-1520
3
S
2x512Kx8 DUALITHIC SRAM
ADVANCED*
WS1M8V-XCX
FEATURES
I
Access Times 17, 20, 25, 35, 45, 55ns
I
Evolutionary, Corner Power/Ground Pinout
I
Packaging:
32 pin, Hermetic Ceramic DIP (Package 300)
I
Organized as two banks of 512Kx8
I
Commercial, Industrial and Military Temperature Ranges
I
3.3V Power Supply
I
Low Power CMOS
I
TTL Compatible Inputs and Outputs
I
Output Enable Internally tied to GND.
* This data sheet describes a product that may or may not be under
development and is subject to change or cancellation without notice.
October 1998
NOTE:
1. CS
1
and CS
2
are used to select the lower and upper 512Kx8 of the
device. CS
1
and CS
2
must not be enabled at the same time.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
V
CC
A15
A17
WE
A13
A8
A9
A11
CS2
A10
CS1
I/O7
I/O6
I/O5
I/O4
I/O3
PIN CONFIGURATION FOR WS1M8V-XCX
32 DIP
TOP VIEW
BLOCK DIAGRAM
512K x 8
512K x 8
A
0-18
WE
CS
1
CS
2
I/O
0-7
(1)
(1)
A
0-18
I/O
0-7
CS
1-2
WE
V
CC
GND
Address Inputs
Data Input/Output
Chip Selects
Write Enable
+3.3V Power Supply
Ground
PIN DESCRIPTION
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WS1M8V-XCX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2X512KX8 Dualithic SRAM Advanced |
| WS1M8-XCX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2X512X8 Dualithic SRAM Preliminary |
| WS1M8-XDJX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SRAM MCP |
| WS1M8-XFX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SRAM MCP |
| WS1M8-XXX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2 x 512K x 8 Dualithic SRAM |
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