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| 型號(hào)： | WS128K32V-25 |
| 英文描述： | 128Kx32 3.3V SRAM Module(128Kx32 ,3.3V,靜態(tài)RAM模塊（存取時(shí)間25ns）) |
| 中文描述： | 128Kx32 3.3靜態(tài)存儲(chǔ)器模塊（128Kx32，3.3伏，靜態(tài)內(nèi)存模塊（存取時(shí)間25ns的）） |
| 文件頁(yè)數(shù)： | 4/8頁(yè) |
| 文件大?。?/td> | 95K |
| 代理商： | WS128K32V-25 |
4
White Microelectronics Phoenix, AZ (602) 437-1520
4
S
WS128K32V-XXX
FIG. 3
AC TEST CIRCUIT
NOTES:
V
Z
is programmable from-2V to +7V.
I
OL
& I
OH
programmable from0 to 16mA.
Tester Impedance Z
0
= 75
.
V
Z
is typically the mdpoint of V
OH
and V
OL
.
I
OL
& I
OH
are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
I
Current Source
D.U.T.
C = 50 pf
I
OL
V
≈
1.5V
(Bipolar Supply)
Z
Current Source
OH
AC TEST CONDITIONS
Parameter
Input Pulse Levels
Input Rise and Fall
Input and Output Reference Level
Output Timing Reference Level
Typ
Unit
V
ns
V
V
V
IL
= 0, V
IH
= 3.0
5
1.5
1.5
AC CHARACTERISTICS
(V
CC
= 3.3V, T
A
= -55
°
C to +125
°
C)
Parameter
Symbol
-15*
-17
-20
-25
-35
Units
Read Cycle
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Read Cycle Time
t
RC
15
17
20
25
35
ns
Address Access Time
t
AA
15
17
20
25
35
ns
Output Hold from Address Change
t
OH
0
0
0
0
0
ns
Chip Select Access Time
t
ACS
15
17
20
25
35
ns
Output Enable to Output Valid
t
OE
10
11
12
15
20
ns
Chip Select to Output in Low Z
t
CLZ
1
5
5
5
5
5
ns
Output Enable to Output in Low Z
t
OLZ
1
5
5
5
5
5
ns
Chip Disable to Output in High Z
t
CHZ
1
8
9
10
12
15
ns
Output Disable to Output in High Z
t
OHZ
1
8
9
10
12
15
ns
1. This parameter is guaranteed by design but not tested.
* Commercial and Industrial only.
AC CHARACTERISTICS
(V
CC
= 3.3V, T
A
= -55
°
C to +125
°
C)
Parameter
Symbol
-15*
-17
-20
-25
-35
Units
Write Cycle
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Write Cycle Time
t
WC
15
17
20
25
35
ns
Chip Select to End of Write
t
CW
13
14
15
20
30
ns
Address Valid to End of Write
t
AW
13
14
15
20
30
ns
Data Valid to End of Write
t
DW
10
11
12
15
18
ns
Write Pulse Width
t
WP
13
14
15
20
30
ns
Address Setup Time
t
AS
0
0
0
0
0
ns
Address Hold Time
t
AH
0
0
0
0
0
ns
Output Active from End of Write
t
OW
1
5
5
5
5
5
ns
Write Enable to Output in High Z
t
WHZ
1
8
9
10
10
15
ns
Data Hold Time
t
DH
0
0
0
0
0
ns
1. This parameter is guaranteed by design but not tested.
* Commercial and Industrial only.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WS128K32V-25G1UC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128Kx32 3.3V SRAM MULTICHIP PACKAGE |
| WS128K32V-25G1UCA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128Kx32 3.3V SRAM MULTICHIP PACKAGE |
| WS128K32V-25G1UI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128Kx32 3.3V SRAM MULTICHIP PACKAGE |
| WS128K32V-25G1UIA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128Kx32 3.3V SRAM MULTICHIP PACKAGE |
| WS128K32V-25G1UM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128Kx32 3.3V SRAM MULTICHIP PACKAGE |
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