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參數(shù)資料
| 型號： | WS128K32NV-25H1M |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | SRAM |
| 英文描述： | 128K X 32 MULTI DEVICE SRAM MODULE, 25 ns, CPGA66 |
| 封裝： | 1.075 X 1.075 INCH, HERMETIC SEALED, CERAMIC, HIP-66 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 462K |
| 代理商： | WS128K32NV-25H1M |
4
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
WS128K32V-XXX
March 2006
Rev. 8
FIGURE 3
– AC TEST CIRCUIT
AC Test Conditions
AC Characteristics
VCC = 3.3V, -55°C ≤ TA ≤ +125°C
Parameter
Write Cycle
Symbol
-15*
-17
-20
-25
-35
Units
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Write Cycle Time
tWC
15
17
20
25
35
ns
Chip Select to End of Write
tCW
13
14
15
20
30
ns
Address Valid to End of Write
tAW
13
14
15
20
30
ns
Data Valid to End of Write
tDW
10
11
12
15
18
ns
Write Pulse Width
tWP
13
14
15
20
30
ns
Address Setup Time
tAS
00000
ns
Address Hold Time
tAH
00000
ns
Output Active from End of Write
tOW1
55555
ns
Write Enable to Output in High Z
tWHZ1
8
9
10
15
ns
Data Hold Time
tDH
00000
ns
1. This parameter is guaranteed by design but not tested.
* Commercial and Industrial only.
I
Current Source
D.U.T.
C
= 50 pf
eff
I OL
V
1.5V
(Bipolar Supply)
Z
Current Source
OH
AC CHARACTERISTICS
VCC = 3.3V, -55°C ≤ TA ≤ +125°C
Parameter
Read Cycle
Symbol
-15*
-17
-20
-25
-35
Units
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Read Cycle Time
tRC
15
17
20
25
35
ns
Address Access Time
tAA
15
17
20
25
35
ns
Output Hold from Address Change
tOH
00000
ns
Chip Select Access Time
tACS
15
17
20
25
35
ns
Output Enable to Output Valid
tOE
10
11
12
15
20
ns
Chip Select to Output in Low Z
tCLZ1
55555
ns
Output Enable to Output in Low Z
tOLZ1
55555
ns
Chip Disable to Output in High Z
tCHZ1
8
9
10
12
15
ns
Output Disable to Output in High Z
tOHZ1
8
9
10
12
15
ns
1. This parameter is guaranteed by design but not tested.
* Commercial and Industrial only.
Notes:
VZ is programmable from -2V to +7V.
IOL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75 .
VZ is typically the midpoint of VOH and VOL.
IOL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
Parameter
Typ
Unit
Input Pulse Levels
VIL = 0, VIH = 3.0
V
Input Rise and Fall
5
ns
Input and Output Reference Level
1.5
V
Output Timing Reference Level
1.5
V
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| WS128K32NV-25H1MA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128Kx32 3.3V SRAM MULTICHIP PACKAGE |
| WS128K32NV-35G1UC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128Kx32 3.3V SRAM MULTICHIP PACKAGE |
| WS128K32NV-35G1UCA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128Kx32 3.3V SRAM MULTICHIP PACKAGE |
| WS128K32NV-35G1UI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128Kx32 3.3V SRAM MULTICHIP PACKAGE |
| WS128K32NV-35G1UIA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128Kx32 3.3V SRAM MULTICHIP PACKAGE |
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