參數(shù)資料
型號(hào): WM8756
廠商: Wolfson Microelectronics
英文描述: 192KHZ SIX CHANNEL SACD COMPATIBLE AUDIO DAC
中文描述: 192kHz的六聲道SACD的兼容的音頻數(shù)模轉(zhuǎn)換器
文件頁數(shù): 24/39頁
文件大?。?/td> 330K
代理商: WM8756
WM8756
Advance Information
AI Rev 1.3 October 2001
24
DAC OUTPUT ATTENUATION
Register bits [7:0] of L0A and R0A control the left and right channel attenuation of DAC 0. Register bits
[7:0] of L1A and R1A control the left and right channel attenuation of DAC 1. Register bits [7:0] of L2A and
R2A control the left and right channel attenuation of DAC 2. Register bits [7:0] of MASTA are a register
that can be used to control attenuation of all channels.
Table 15 shows how the attenuation levels are selected from the 8-bit words.
AX[7:0]
00(hex)
01(hex)
:
:
:
FE(hex)
FF(hex)
ATTENUATION LEVEL
-
dB (mute)
-127.5dB
:
:
:
-0.5dB
0dB
Table 15 Attenuation Control Levels
EXTENDED INTERFACE CONTROL
It is possible to run the WM8756 channels at different rates with the front two channels running at twice
the rate of the rear four channels. In this mode which is enabled by bit 0 of register 9, the interface runs
at the faster data rate but pin 13 acts as the framing LRCIN for the rear channels see Figure 11.
REGISTER ADDRESS
0001001
Split rate mode
BIT
0
LABEL
DEFAULT
DESCRIPTION
2SPD
0
Activates the split rate mode
0: Normal operation.
1: Split rate operation.
When the WM8756 receives updates to the volume levels it will, by default, wait for the signal to pass
through midrail before applying the change to the output. This ensures that minimal distortion is seen on
the output when the volume is changed. This function applies individually to each channel.
REGISTER ADDRESS
0001001
Zero crossing detect
BIT
1
LABEL
DEFAULT
DESCRIPTION
ZCD
0
Controls the ZCD
0: Enabled.
1: Disabled.
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