參數(shù)資料
型號(hào): WM8728
廠商: Wolfson Microelectronics
英文描述: 24-bit, 192kHz Stereo DAC with Volume Control and DSD Support
中文描述: 24位,192kHz立體聲DAC,具有音量控制和渠務(wù)署支持
文件頁數(shù): 14/28頁
文件大?。?/td> 266K
代理商: WM8728
WM8728
Product Preview
WOLFSON MICROELECTRONICS LTD
PP Rev 1.2 April 2001
14
DSP LATE MODE
In DSP late mode, the first bit is sampled on the BCKIN rising edge, which detects a low to high
transition on LRCIN. No BCKIN edges are allowed between the data words. The word order is
DIN left, DIN right.
LRCIN
BCKIN
DIN
Input Word Length (IWL)
1/fs
LEFT CHANNEL
n
2
1
n-1
LSB
MSB
n
2
1
n-1
RIGHT CHANNEL
NO VALID DATA
1
Figure 11 DSP Late Mode Timing Diagram
AUDIO DATA SAMPLING RATES
The master clock for WM8728 can range from 128fs to 768fs, where fs is the audio sampling
frequency (LRCIN) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz. The master clock is used
to operate the digital filters and the noise shaping circuits.
The WM8728 has a master clock detection circuit that automatically determines the relationship
between the master clock frequency and the sampling rate (to within +/- 32 system clocks). If
there is a greater than 32 clocks error, the interface shuts down the DAC and mutes the output.
The master clock should be synchronised with LRCIN, although the WM8728 is tolerant of phase
differences or jitter on this clock. See Table 1
MASTER CLOCK FREQUENCY (MHZ) (MCLK)
SAMPLING
RATE
(LRCIN)
32kHz
44.1kHz
48kHz
96kHz
192kHz
Table 1 Typical Relationships Between Master Clock Frequency and Sampling Rate
128fs
192fs
256fs
384fs
512fs
768fs
4.096
5.6448
6.114
12.288
24.576
6.144
8.467
9.216
18.432
36.864
8.192
11.2896
12.288
24.576
Unavailable
12.288
16.9340
18.432
36.864
Unavailable
16.384
22.5792
24.576
Unavailable
Unavailable
24.576
33.8688
36.864
Unavailable
Unavailable
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