參數(shù)資料
型號(hào): WM8716
廠商: Wolfson Microelectronics
英文描述: High Performance 24-bit, 192kHz Stereo DAC
中文描述: 高性能24位,192kHz的立體聲DAC
文件頁(yè)數(shù): 12/21頁(yè)
文件大小: 351K
代理商: WM8716
WM8716
Production Data
WOLFSON MICROELECTRONICS LTD
PD Rev 3.1 April 2001
12
DAC OUTPUT ATTENUATION
The level of attenuation for eight bit code X, is given by:
0.5
(X - 255) dB, 1
X
255
-
dB (mute),
X = 0
Bit 8 in register 0 (LDL) is used to control the loading of attenuation data in B[7:0]. When LDL is set
to 0, attenuation data will be loaded into AL[7:0], but it will not affect the filter attenuation. LDR in
register 1 has the same function for right channel attenuation. Only when LDL or LDR is set to
1
will
the filter attenuation be updated. This permits left and right channel attenuation to be updated
simultaneously.
Attenuation level is controlled by AL[7:0] (left channel) or AR[7:0] (right channel). Attenuation levels
are given in Table 4.
X[7:0]
00(hex)
01(hex)
:
:
FD(hex)
FE(hex)
FF(hex)
ATTENUATION LEVEL
-
dB (mute)
-127.0dB
:
:
-1.0dB
-0.5dB
0.0dB
Table 7 Attenuation Control Level
Bit 2 in Reg3 is used to control the attenuator (ATC). When ATC is
high
, the attenuation data
loaded in program register 0 is used for both the left and the right channels. When ATC is low, the
attenuation data for each register is applied separately to left and right channels.
SOFT MUTE
MUT
(REG2, B0)
L
H
Table 8 Soft Mute
Soft Mute off (normal operation)
Soft Mute on (no output)
Setting MUT causes the attenuation to ramp from the current value down to 00. The values held in
the attenuation registers are unchanged. When MUT is reset the attenuation will ramp back up to the
previous value. The ramp rate is 128/fs s/0.5dB step.
DIGITAL DE-EMPHASIS
DEM
(REG2, B1)
L
H
Table 9 Digital De-Emphasis
De-emphasis off
De-emphasis on
DAC OPERATION ENABLE
OPE
(REG2,B2)
L
H
Normal operation
DAC output forced to bipolar zero,
irrespective of input data.
Table 10 DAC Operation Enable
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