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參數(shù)資料
| 型號： | WM8146 |
| 廠商： | Wolfson Microelectronics |
| 英文描述： | TVS 400W 40A UNIDIRECT SMA |
| 中文描述： | 12位（8 4位）線性傳感器圖像處理器 |
| 文件頁數(shù)： | 15/17頁 |
| 文件大?。?/td> | 195K |
| 代理商： | WM8146 |
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WM8146
WOLFSON MICROELECTRONICS LTD
PP Rev 1.1 January 2000
15
REGISTER MAP DESCRIPTION
REGISTER
BIT
NO
0
1
BIT NAME(S)
DEFAULT
DESCRIPTION
ENADC
CDS
1
1
ADC standby control : 0=standby, 1=active
Select correlated double sampling mode:
0=single ended mode, 1=CDS mode
Mono/colour select: 0=colour, 1=monchrome operation
Required when VSMP at 6MSPS:
0=other mode, 1=VSMP at 6MSPS
Digitally inverts the polarity of input data.
0= negative going video gives negative going output,
1=negative-going video gives positive going output data.
Reset Level Clamp Voltage:
00 = 1.5V; 01 = 2.5V; 10 = 1.5V; 11 = Reserved
CDS mode reset timing adjust
00 = advance 1 MCLK period
01 = Normal
10 = Retard 1 MCLK period
11 = Retard 2 MCLK periods
Monochrome mode channel select
00 = Red channel select
01 = Green channel select
10 = Blue channel select
11 = Reserved
Write any value to the Software Reset register to cause all
cells to be reset.
Offset DAC Output Range:
0 = DAC Output range =VMID/2 = +/-1.25V
1 = DAC output Range = 1.5*VMID/2 = +/-1.875V
Polarity of Offset DAC output
0 = Positive Output (Offset added)
1 = Negative Output (Offset removed)
2
6
MONO
VSMP6M
0
0
Setup
Register 1
Setup
Register 2
2
INVOP
0
1:0
RLC[1:0]
01
5:4
CDSREF[1:0]
01
Setup
Register 3
7:6
CHAN[1:0]
00
Software
Reset
Setup
Register 4
1
DACRNG
0
Registers
100100 to
100111
0
DSIGN
0
Table 3 Register Control Bits
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