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參數(shù)資料
| 型號： | WM2638ID |
| 廠商： | Wolfson Microelectronics |
| 英文描述： | TVS UNI 225W 6V PWRDI 123 SMD |
| 中文描述： | 雙路12位串行輸入電壓輸出DAC，帶有內(nèi)部參考 |
| 文件頁數(shù)： | 7/11頁 |
| 文件大小： | 360K |
| 代理商： | WM2638ID |
WM2638
Production Data
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 July 99
7
DEVICE DESCRIPTION
GENERAL FUNCTION
The device uses a resistor string network buffered with an op amp to convert 12-bit digital data to
analogue voltage levels (see Block Diagram). The output voltage is determined by the reference
input voltage and the input code according to the following relationship:
Output voltage =
(
)
4096
CODE
V
2
REF
INPUT
1111
OUTPUT
)
1111
1111
(
4096
4095
V
2
REF
:
:
1000
0000
0001
(
)
4096
2049
V
2
REF
1000
0000
0000
(
)
REF
REF
V
4096
)
2048
V
2
=
0111
1111
1111
(
4096
2047
V
2
REF
:
:
0000
0000
0001
(
)
4096
1
V
2
REF
0000
0000
0000
0V
Table 1 Binary Code Table (0V to 2V
REF
Output), Gain = 2
POWER ON RESET
An internal power-on-reset circuit resets the DAC registers to all 0s on power-up.
BUFFER AMPLIFIER
The output buffer has a near rail-to-rail output with short circuit protection and can reliably drive a
2k
load with a 100pF load capacitance.
SERIAL INTERFACE
When chip select (NCS) is low, the input data is read into a 16-bit shift register with the input data
clocked in most significant bit first. The falling edge of the SCLK input shifts the data into the input
register. After 16 bits have been transferred, the next rising edge on SCLK or NCS then transfers
the data to the DAC latch. When NCS is high, input data cannot be clocked into the input register
(see Table 2).
SERIAL CLOCK AND UPDATE RATE
Figure 1 shows the device timing. The maximum serial rate is:
1
min
WCL
min
WCH
+
f
SCLK
max =
MHz
20
t
t
=
The digital update rate is limited to an 800ns period, or 1.25MHz frequency. However, the DAC
settling time to 12 bits limits the update rate for large input step transitions.
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