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參數(shù)資料
| 型號(hào)： | WM2638CD |
| 廠商： | Wolfson Microelectronics |
| 英文描述： | Dual 12-Bit Serial Input Voltage Output DAC with Internal reference |
| 中文描述： | 雙路12位串行輸入電壓輸出DAC，帶有內(nèi)部參考 |
| 文件頁數(shù)： | 9/11頁 |
| 文件大?。?/td> | 360K |
| 代理商： | WM2638CD |
WM2638
Production Data
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 July 99
9
Examples:
1.
Set internal reference voltage to 2.048V
D15
1
D14
x
D13
0
D12
1
D11
x
D10
x
D9
x
D8
x
D7
x
D6
x
D5
x
D4
x
D3
x
D2
x
D1
1
D0
0
2.
Write new DAC A value and update DAC A output
D15
0
D14
x
D13
0
D12
0
D11
D10
D9
D8
D7
New DAC A output value
D6
D5
D4
D3
D2
D1
D0
FUNCTION OF THE LATCH CONTROL BITS (D15 AND D12)
PURPOSE AND USE OF THE DOUBLE BUFFER
Normally only one DAC output can change after a write. The double buffer allows both DAC outputs
to change after a single write. This is achieved by the two following steps.
A double buffer only write is executed to store the new DAC B data without changing the DAC A
and B outputs.
Following the previous step, a write to latch A is executed. This writes the serial interface register
(SIR) data to latch A and also writes the double buffer contents to latch B. Thus both DACs
receive their new data at the same time and so both DAC outputs begin to change at the same
time.
Unless a double buffer only write is issued, the latch B and double buffer contents are identical.
Thus, following a write to latch A or B with another write to latch A does not change the latch B
contents.
Three data transfer options are possible. All transfers occur immediately after NCS goes high (or on
the sixteenth positive SCLK edge, whichever is earlier) and are described in the following sections).
LATCH A WRITE, LATCH B UPDATE (D15 = HIGH, D12 = LOW)
The serial interface register (SIR) data are written to latch A and the double buffer latch contents
are written to latch B. The double buffer contents are unaffected. This program bit condition allows
simultaneous output updates of both DACs.
SERIAL
INTERFACE
REGISTER
D12 = LOW
D15 = HIGH
DOUBLE
BUFFER LATCH
LATCH B
TO DAC B
LATCH A
TO DAC A
Figure 2 Latch A Write, Latch B Update
LATCH B AND DOUBLE BUFFER 1 WRITE (D15 = LOW, D12 = LOW)
The SIR data are written to both latch B and the double buffer. Latch A is unaffected.
SERIAL
INTERFACE
REGISTER
D12 = LOW
D15 = LOW
DOUBLE
BUFFER LATCH
LATCH B
TO DAC B
LATCH A
TO DAC A
Figure 3 Latch B and Double Buffer Write
DOUBLE BUFFER ONLY WRITE (D15 = LOW, D12 = HIGH)
The SIR data are written to the double buffer only. Latch A and B contents are unaffected.
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