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參數(shù)資料
| 型號(hào)： | WM2637CD |
| 廠商： | Wolfson Microelectronics |
| 英文描述： | Dual 10-Bit Serial Input Voltage Output DAC with Internal Reference |
| 中文描述： | 雙路10位串行輸入電壓輸出DAC，帶有內(nèi)部參考 |
| 文件頁(yè)數(shù)： | 4/11頁(yè) |
| 文件大小： | 262K |
| 代理商： | WM2637CD |
WM2637
Production Data
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 July 99
4
Test Conditions:
R
L
= 10k
, C
L
= 100pF. VDD
= 5V
±
10%, V
REF
= 2.048V and VDD
= 3V
±
10%, V
REF
= 1.024V over recommended operating free-air
temperature range (unless noted otherwise)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
See Note 12
Total harmonic distortion
THD
fs
= 400ksps, f
OUT
= 1kHz,
BW = 20kHz
See Note 12
fs
= 400ksps, f
OUT
= 1kHz,
BW = 20kHz
See Note 12
-61
-50
dB
Spurious free dynamic range
SPFDR
51
62
dB
Reference Configured As Input
Reference input resistance
R
REFIN
10
M
Reference input capacitance
C
REFIN
55
pF
Reference feedthrough
V
REF
= 1VPP at 1kHz
+ 1.024V dc, DAC code 0
V
REF
= 0.2VPP + 1.024V dc
DAC code 1024
Slow
Fast
-60
dB
Reference input bandwidth
1.0
1.0
MHz
MHz
Reference Configured As Output
Low reference voltage
V
REFOUTL
1.003
1.024
1.045
V
High reference voltage
V
REFOUTH
VDD > 4.75V
2.027
2.048
2.069
V
Output source current
I
REFSRC
1
mA
Output sink current
I
REFSNK
-1
mA
Load Capacitance
100
pF
PSRR
-48
dB
Digital Inputs
High level input current
I
IH
Input voltage = VDD
1
μ
A
Low level input current
I
IL
Input voltage = 0V
-1
μ
A
Input capacitance
C
I
8
pF
Notes:
1.
Integral non-linearity (INL)
is the maximum deviation of the output from the line between zero and full scale (excluding the
effects of zero code and full scale errors).
Differential non-linearity (DNL)
is the difference between the measured and ideal 1LSB amplitude change of any adjacent two
codes. A guarantee of monotonicity means the output voltage changes in the same direction (or remains constant) as a change
in digital input code.
Zero code erro
r is the voltage output when the DAC input code is zero.
Gain error
is the deviation from the ideal full scale output excluding the effects of zero code error.
Power supply rejection ratio
is measured by varying VDD from 4.5V to 5.5V and measuring the proportion of this signal
imposed on the zero code error and the gain error.
Zero code error
and
Gain error
temperature coefficients are normalised to full scale voltage.
Output load regulation
is the difference between the output voltage at full scale with a 10k
load and 2k
load. It is
expressed as a percentage of the full scale output voltage with a 10k
load.
I
DD
is measured while continuously writing code 1512 to the DAC. For V
IH
< VDD - 0.7V and V
IL
> 0.7V supply current will
increase.
Typical supply current
in power down mode is 10nA. Production test limits are wider for speed of test.
Slew rate
results are for the lower value of the rising and falling edge slew rates
Settling time
is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and falling
edges. Limits are ensured by design and characterisation, but are not production tested.
SNR, SNRD, THD
and
SPFDR
are measured on a synthesised sinewave at frequency f
OUT
generated with a sampling
frequency fs
.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
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