參數(shù)資料
型號: WM2637
廠商: Wolfson Microelectronics
英文描述: Dual 10-Bit Serial Input Voltage Output DAC with Internal Reference
中文描述: 雙路10位串行輸入電壓輸出DAC,帶有內(nèi)部參考
文件頁數(shù): 10/11頁
文件大?。?/td> 262K
代理商: WM2637
WM2637
Production Data
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 July 99
10
DOUBLE BUFFER ONLY WRITE (D15 = LOW, D12 = HIGH)
The SIR data are written to the double buffer only. Latch A and B contents are unaffected.
SERIAL
INTERFACE
REGISTER
D12 = HIGH
D15 = LOW
DOUBLE
BUFFER
LATCH B
TO DAC B
LATCH A
TO DAC A
Figure 9 Double Buffer Only Write
OPERATIONAL EXAMPLES
1. changing the latch A data from zero to full code
Assuming that latch A starts at zero code (e.g. after power up), the latch can be filled with 1s by
writing (bit D15 on the left, D0 on the right)
1X00 1111 1111 11xx
to the serial interface. Bit D14 can be zero to select slow mode or one to select fast mode.
The latch B contents and DAC B output are not changed by this write unless the double buffer
contents are different from the latch B contents. This can only be true if the last write was a double
buffer-only write.
2. changing the latch B data from zero to full code
Assuming that latch B starts at zero code (e.g. after power up), the latch can be filled with 1s by
writing (bit D15 on the left, D0 on the right)
0X00 1111 1111 11xx
to the serial interface. Bit D14 can be zero to select slow mode or one to select fast mode. The data
(bits D2 to D11) are written to both the double buffer and latch B.
The latch A contents and the DAC A output are not changed by this write.
3. double buffered change of both DAC outputs
Assuming that DACs A and B start at zero code (e.g. after power up), if DAC A is to be driven to
mid-scale and DAC B to full-scale, and if the outputs are to begin rising at the same time, this can
be achieved as follows:
First,
0d01 1111 1111 11xx
is written (bit D15 on the left, D0 on the right) to the serial interface. This loads the full-scale code
into the double buffer but does not change the latch B contents and the DAC B output voltage. The
latch A contents and the DAC A output are also unaffected by this write operation.
Changing from fast to slow to fast mode changes the supply current which can glitch the outputs,
and so D14 (designated by d in the above data word) should be set to maintain the speed mode set
by the previous write.
Next,
1d00 1000 0000 00xx
is written (bit D15 on the left, D0 on the right) to the serial interface. This writes the mid-scale code
(1000000000) to latch A and also copies the full-scale code from the double buffer to latch B. Both
DAC outputs thus begin to rise after the second write.
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