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參數(shù)資料
| 型號(hào)： | WM2623ID |
| 廠商： | Wolfson Microelectronics |
| 英文描述： | Low Power 8-bit Serial Input DAC |
| 中文描述： | 低功耗8位串行輸入DAC |
| 文件頁(yè)數(shù)： | 5/10頁(yè) |
| 文件大?。?/td> | 86K |
| 代理商： | WM2623ID |
Production Data
WM2623
WOLFSON MICROELECTRONICS LTD
PD
Rev 1.0 October 2000
5
SERIAL INTERFACE
NCS
FS
SCLK
DIN
1
2
3
4
5 15
16
D0
D1
D12
D13
D14
D15
t
WL
t
WH
t
SUD
t
HD
t
SUCSFS
t
SUC16CS
t
WHFS
t
SUFSCLK
t
SUC16FS
Figure 1 Timing Diagram
Test Conditions:
R
L
= 10k
, C
L
= 100pF. VDD
= 5V ±10%, V
REF
= 2.048V and VDD
= 3V ±10%, V
REF
= 1.024V over recommended operating
free-air temperature range (unless noted otherwise).
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
SUCSFS
Setup time NCS low before falling FS edge.
10
ns
t
SUFS
Setup time FS low before first falling SCLK edge.
Setup time, 16
th
falling SCLK edge after FS low on
which data bit D0 is sampled before rising edge of FS.
Setup time, 16
th
rising SCLK edge (first after data bit
D0 sampled) before NCS rising edge. If FS is used
instead of the 16
rising edge to update the DAC, this
setup time is between the FS rising edge and the NCS
rising edge.
Pulse duration, SCLK high.
8
ns
t
SUC16FS
10
ns
t
SUC16CS
10
ns
t
WH
25
ns
t
WL
Pulse duration, SCLK low.
25
ns
t
SUD
Setup time, data ready before SCLK falling edge.
8
ns
t
HD
Hold time, data held valid after SCLK falling edge.
5
ns
t
WHFS
Pulse duration, FS high.
20
ns
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