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參數(shù)資料
| 型號(hào)： | WM2623CD |
| 廠(chǎng)商： | Wolfson Microelectronics |
| 英文描述： | Low Power 8-bit Serial Input DAC |
| 中文描述： | 低功耗8位串行輸入DAC |
| 文件頁(yè)數(shù)： | 8/10頁(yè) |
| 文件大小： | 86K |
| 代理商： | WM2623CD |
WM2623
Production Data
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 October 2000
8
SERIAL CLOCK AND UPDATE RATE
Figure 1 shows the device timing. The maximum serial clock rate is:
MHz
t
t
f
WL
WH
SCLK
20
1
+
min
min
max
=
=
Since a data word contains 16 bits, the sample rate is limited to
(
)
MHz
t
t
f
WL
WH
s
25
.
16
1
min
min
max
=
+
=
However, the DAC settling time to 8 bits accuracy limits the response time of the analogue output
for large input step transitions.
SOFTWARE CONFIGURATION OPTIONS
Table 2 shows the composition of a 16 bit data word. D11-D4 contains the 8-bit data word, and
D14-D13 hold the programmable options. Bits D15, D12, and D3 through D0 should be set to
ZERO.
D15
0
Table 2 Register Map
D14
SPD PWR
D13
D12
0
D11
D10
D9
New DAC value (8 bits)
D8
D7
D6
D5
D4
D3
0
D2
0
D1
0
D0
0
PROGRAMMABLE SETTLING TIME
SPD (Bit 14) allows for software control of the converter speed. A ONE selects the fast mode,
where typical settling time to within
±
0.5LSB of the final value is 3
μ
s. a ZERO puts the device into
the slow mode, where typical settling time is 9
μ
s.
PROGRAMMABLE POWER DOWN
The power down function is controlled by PWR (Bit 13). A ZERO configures the device as active,
or fully powered up, a ONE configures the device into power down mode. When the power down
function is released the device reverts to the DAC code set prior to power down.
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| WM2623ID | 制造商:WOLFSON 制造商全稱(chēng):WOLFSON 功能描述:Low Power 8-bit Serial Input DAC |
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| WM2625CD | 制造商:WOLFSON 制造商全稱(chēng):WOLFSON 功能描述:Low Power Dual 8-bit Serial Input DAC |
| WM2625ID | 制造商:WOLFSON 制造商全稱(chēng):WOLFSON 功能描述:Low Power Dual 8-bit Serial Input DAC |
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