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參數(shù)資料
| 型號(hào)： | WF8M32-150G4DM5 |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | PROM |
| 英文描述： | 8M X 32 FLASH 5V PROM MODULE, 150 ns, CQFP68 |
| 封裝： | 40 X 40 MM, 5.20 MM HEIGHT, HERMETIC SEALED, CERAMIC, QFP-68 |
| 文件頁(yè)數(shù)： | 1/10頁(yè) |
| 文件大小： | 350K |
| 代理商： | WF8M32-150G4DM5 |
1
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WF8M32-XG4DX5
October 1999
Rev. 3
ADVANCED*
White Electronic Designs Corp. reserves the right to change products or specications without notice.
8Mx32 5V FLASH MODULE
FEATURES
Access Time of 100, 120, 150ns
Packaging:
68 Lead, 40 mm (1.560") square hermetic CQFP,
5.2 mm (0.205") high (Package 503)
Sector Architecture
32 equal size sectors of 64KBytes per each 2Mx8
chip
Any combination of sectors can be erased. Also
supports full chip erase.
100,000 Write/Erase Cycles Minimum
Organized as 8Mx32
Commercial, Industrial, and Military Temperature
Ranges
5 Volt Read and Write. 5V ± 10% Supply.
Low Power CMOS
Data# Polling and Toggle Bit feature for detection of
program or erase cycle completion.
Supports reading or programming data to a sector
not being erased.
RESET# pin resets internal state machine to the
read mode. (Not available in HIP package for
WF2M32-XHX5)
Built-in Decoupling Caps and Multiple Ground Pins
for Low Noise Operation, Seperate Power and
Ground Planes to improve noise immunity.
Built in Buffering.
* This product is under development, is not qualied or characterized and is subject to
change or cancellation without notice.
Note: For programming information refer to Flash Programming 16M5 Application Note.
PIN DESCRIPTION
I/O0-31
Data Inputs/Outputs
A0-22
Address Inputs
WE
Write Enable
CS1-4
Chip Selects
OE
Output Enable
VCC
Power Supply
RESET
Reset
GND
Ground
NC
Not Connected
FIGURE 1 – PIN CONFIGURATIONFOR
WF8M32-XG4DX5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
9
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
GND
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
VCC
A1
1
A12
A13
A14
A15
A16
CS2#
OE#
CS4#
A17
A18
A19
A20
A21
RESET#
A22
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
NC
A0
A1
A2
A3
A4
A5
CS1#
GND
CS3#
WE#
A6
A7
A8
A9
A10
VCC
BLOCK DIAGRAM
Top View
2M x 8
I/O0-31
Interface
1
4
1
23
1
4
1
23
CS1#
8
I/O 0-7
8
I/O 8-15
8
I/O 16-23
8
I/O 24-31
CS2#
CS3#
CS4#
32
RESET#
CS1-4#
WE#
OE#
A0-22
CS1# selects I/O0-7, CS2# selects I/O8-15, CS3# selects I/O16-23, CS4# selects I/O24-31
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