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參數(shù)資料
| 型號： | WEDPZ512K72S-133BC |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | SRAM |
| 英文描述： | 512K X 72 MULTI DEVICE SRAM MODULE, 4.2 ns, PBGA152 |
| 封裝： | 17 X 23 MM, PLASTIC, BGA-152 |
| 文件頁數(shù)： | 1/15頁 |
| 文件大?。?/td> | 433K |
| 代理商： | WEDPZ512K72S-133BC |
WEDPZ512K72S-XBX
1
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
PRELIMINARY*
White Electronic Designs Corp. reserves the right to change products or specications without notice.
November 2003
Rev. 6
Fast clock speed: 150, 133, and 100MHz
Fast access times: 3.8ns, 4.2ns, and 5.0ns
Fast OE# access times: 3.8ns, 4.2ns, and 5.0ns
High performance 3-1-1-1 access rate
2.5V ± 5% power supply
Common data inputs and data outputs
Byte write enable and global write control
Six chip enables for depth expansion and address
pipeline
Internally self-timed write cycle
Burst control pin (interleaved or linear burst
sequence)
Automatic power-down for portable applications
Commercial, industrial and military temperature
ranges
Packaging:
152 PBGA package 17 x 23mm
512K x 72 SYNCHRONOUS PIPELINE BURST ZBL SRAM
FEATURES
DESCRIPTION
BENEFITS
30% space savings compared to equivalent TQFP
solution
Reduced part count
24% I/O reduction
Laminate interposer for optimum TCE match
Low Prole
Reduce layer count for board routing
Suitable for hi-reliability applications
User congurable as 1M x 36 or 2M x 18
Upgradable to 1M x 72 (contact factory for
availability)
The WEDC SyncBurst - SRAM employs high-speed,
low-power CMOS design that is fabricated using an
advanced CMOS process. WEDC’s 32Mb SyncBurst
SRAMs integrate two 512K x 36 SSRAMs into a single
BGA package to provide 512K x 72 conguration. All
synchronous inputs pass through registers controlled by a
positive-edge-triggered single-clock input (CLK). The ZBL
or Zero Bus Latency Memory utilizes all the bandwidth
in any combination of operating cycles. Address, data
inputs, and all control signals except output enable and
linear burst order are synchronized to input clock. Burst
order control must be tied “High or Low.” Asynchronous
inputs include the sleep mode enable (ZZ). Output Enable
controls the outputs at any given time. Write cycles are
internally self-timed and initiated by the rising edge of the
clock input. This feature eliminates complex off-chip write
pulse generation and provides increased timing exibility
for incoming signals.
* This product is under development, is not qualied or characterized and is subject to
change without notice.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WEDPZ512K72S-133BI | 制造商:Microsemi Corporation 功能描述:512K X 72 ZBL SSRAM MODULE, 2.5V, 133MHZ, 152 BGA 17MM X 23M - Bulk |
| WEDPZ512K72S-133BM | 制造商:Microsemi Corporation 功能描述:512K X 72 ZBL SSRAM MODULE, 2.5V, 133MHZ, 152 BGA 17MM X 23M - Bulk |
| WEDPZ512K72S-150BC | 制造商:Microsemi Corporation 功能描述:512K X 72 ZBL SSRAM MODULE, 2.5V, 150MHZ, 152 BGA 17MM X 23M - Bulk |
| WEDPZ512K72S-150BI | 制造商:Microsemi Corporation 功能描述:512K X 72 ZBL SSRAM MODULE, 2.5V, 150MHZ, 152 BGA 17MM X 23M - Bulk |
| WEDPZ512K72S-150BM | 制造商:Microsemi Corporation 功能描述:512K X 72 ZBL SSRAM MODULE, 2.5V, 150MHZ, 152 BGA 17MM X 23M - Bulk |
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