參數(shù)資料
型號(hào)： WEDPNF8M721V-1012BC
元件分類： 存儲(chǔ)器
英文描述： SPECIALTY MEMORY CIRCUIT, PBGA275
封裝： 32 X 25 MM, PLASTIC, BGA-275
文件頁(yè)數(shù)： 15/42頁(yè)
文件大?。?/td> 686K
代理商： WEDPNF8M721V-1012BC
22
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WEDPNF8M721V-XBX
and addresses are no longer latched.
Figure 7 illustrates the algorithm for the erase operation. See the
Erase/Program Operations tables in “Flash AC Characteristics”
for parameters, and to Figure 13 for timings diagram.
SECTOR ERASE COMMAND SEQUENCE
Sector erase is six bus cycle operation. The sector erase command
sequence is initiated by writing two unlock cycles, followed by a
setup command. Two additional unlock write cycles are then
followed by the address of the sector to be erased, and the sector
erase command, which in turn invokes the Embedded Erase algorithm.
Table 7 shows the address and data requirements for the sector
erase command sequence.
The device does
not require the system to preprogram the memory
prior to erase. The Embedded Erase algorithm automatically programs
and verifies the entire memory for an all zero data pattern prior to
electrical erase. The system is not required to provide any controls
or timings during these operations.
After the command sequence is written, a sector erase time-out
of 50
s begins. During the time-out period, additional sector
addresses and sector erase commands may be written. Loading
the sector erase buffer may be done in any sequence, and the
number of sectors may be from one sector to all sectors. The time
between these additional cycles must be less than 50
s, otherwise
the last address and command might not be accepted, and erasure
may begin. It is recommended that processor interrupts can be re-
enabled after the last Sector Erase command is written. If the time
between additional sector erase commands can be assumed to be
less than 50
s, the system need not monitor FD3. Any command
other than the Sector Erase or Erase Suspend during the
time-out period resets the device to reading array data. The
system must rewrite the command sequence and any additional
sector addresses and commands.
The system can monitor FD3 to determine if the sector erase timer
has timed out. See the “FD3: Sector Erase Timer” section. The
time-out begins from the rising edge of the final FWE pulse in
command sequence.
Once the sector erase operation has begun, only the Erase Suspend
command is valid. All other command is valid. All other commands
are ignored. Note that a hardware reset during the sector erase
operation. The Sector Erase command sequence should be reinitiated
once the device has returned to reading array data, to ensure data
integrity.
When the Embedded Erase algorithm is complete, the device
returns to reading array data and addresses are no longer latched.
The system can determine the status of the erase operation by
using FD7, FD6, or FD2, or RY/BY1. See “Write Operation Status”
for information on these status bits.
Figure 7 illustrates the algorithm for the erase operation. See the
Erase/Program Operations tables in the “Flash AC Characteristics”
for parameters, and to Figure 13 for timings diagram.
FIG. 7
ERASE OPERATION
Start
Write Erase
Command Sequence
Data Poll from System
Erasure Completed
No
Data = FFh
?
Yes
Embedded
Erase
Algorithm
in progress
1. See Table 5 for erase command sequence.
2. See "FD3 : Sector Erase Timer" for more information.
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