參數(shù)資料
型號(hào)： WEDPN8M72V-XBX
英文描述： SDRAM MCP
中文描述： SDRAM的MCP的
文件頁(yè)數(shù)： 1/14頁(yè)
文件大?。?/td> 203K
代理商： WEDPN8M72V-XBX
1
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WEDPN4M72V-X BX
November 2003 Rev. 14
The 32MByte (256Mb) SDRAM is a high-speed CMOS, dy-
namic random-access ,memory using 5 chips containing
67,108,864 bits. Each chip is internally configured as a quad-
bank DRAM with a synchronous interface. Each of the chip’s
16,777,216-bit banks is organized as 4,096 rows by 256
columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a pro-
grammed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVE com-
mand, which is then followed by a READ or WRITE com-
mand. The address bits registered coincident with the AC-
TIVE command are used to select the bank and row to be
accessed (BA0, BA1 select the bank; A0-11 select the row).
The address bits registered coincident with the READ or
WRITE command are used to select the starting column lo-
cation for the burst access.
The SDRAM provides for programmable READ or WRITE burst
lengths of 1, 2, 4 or 8 locations, or the full page, with a
burst terminate option. An AUTO PRECHARGE function may
be enabled to provide a self-timed row precharge that is
initiated at the end of the burst sequence.
The 256Mb SDRAM uses an internal pipelined architecture
to achieve high-speed operation. This architecture is com-
patible with the 2n rule of prefetch architectures, but it also
allows the column address to be changed on every clock
cycle to achieve a high-speed, fully random access.
Precharging one bank while accessing one of the other three
banks will hide the precharge cycles and provide seam-
less, high-speed, random-access operation.
4Mx72 Synchronous DRAM
!
High Frequency = 100, 125MHz
Package:
219 Plastic Ball Grid Array (PBGA), 25 x 21mm
Single 3.3V ± 0.3V power supply
Fully Synchronous; all signals registered on positive
edge of system clock cycle
Internal pipelined operation; column address can be
changed every clock cycle
Internal banks for hiding row access/precharge
Programmable Burst length 1,2,4,8 or full page
4096 refresh cycles
Commercial, Industrial and Military Temperature Ranges
Organized as 4M x 72
Weight: WEDPN4M72V-XBX - 2 grams typical
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60% SPACE SAVINGS
Reduced part count
Reduced I/O count
19% I/O Reduction
Lower inductance and capacitance for low noise
performance
Suitable for hi-reliability applications
Upgradeable to 8M x 72 density with same footprint
(contact factory for information)
*This product is subject to change without notice.
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FEATURES
BENEFITS
GENERAL DESCRIPTION
25
21
Discrete Approach
11.9
11.9
S
A
V
I
N
G
S
Area
I/O
Count
5 x 265mm
2
= 1328mm
2
525mm
2
60%
5 x 54 pins = 270 pins
219 Balls
19%
ACTUAL SIZE
22.3
11.9
11.9
11.9
54
TSOP
54
TSOP
54
TSOP
54
TSOP
54
TSOP
White Electronic Designs
WEDPN4M72V-XBX
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
WEDPNF8M721V-1010BC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package
WEDPNF8M721V-1010BI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package
WEDPNF8M721V-1010BM 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package
WEDPNF8M721V-1012BC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package
WEDPNF8M721V-1012BI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package
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