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參數(shù)資料
| 型號(hào)： | WEDPN8M72V-133BC |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 8M X 72 SYNCHRONOUS DRAM MODULE, 5.4 ns, DMA270 |
| 封裝： | DIMM-270 |
| 文件頁(yè)數(shù)： | 1/12頁(yè) |
| 文件大?。?/td> | 311K |
| 代理商： | WEDPN8M72V-133BC |
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White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WEDPN8M72V-133BC
November 2003 Rev. 4
GENERAL DESCRIPTION
The 64MByte (512Mb) SDRAM is a high-speed CMOS, dynamic
random-access ,memory using 5 chips containing 134,217,728
bits. Each chip is internally congured as a quad-bank DRAM
with a synchronous interface. Each of the chip’s 33,554,432-bit
banks is organized as 4,096 rows by 512 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVE command,
which is then followed by a READ or WRITE command. The
address bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed (BA0,
BA1 select the bank; A0-11 select the row). The address bits
registered coincident with the READ or WRITE command are
used to select the starting column location for the burst access.
The SDRAM provides for programmable READ or WRITE burst
lengths of 1, 2, 4 or 8 locations, or the full page, with a burst
terminate option. An AUTO PRECHARGE function may be
enabled to provide a self-timed row precharge that is initiated
at the end of the burst sequence.
The 512Mb SDRAM uses an internal pipelined architecture to
achieve high-speed operation. This architecture is compatible
with the 2n rule of prefetch architectures, but it also allows the
column address to be changed on every clock cycle to achieve
a high-speed, fully random access. Precharging one bank while
accessing one of the other three banks will hide the precharge
cycles and provide seamless, high-speed, random-access
operation.
The 512Mb SDRAM is designed to operate in 3.3V, low-power
memory systems. An auto refresh mode is provided, along with
a power-saving, power-down mode.
All inputs and outputs are LVTTL compatible. SDRAMs
offer substantial advances in DRAM operating performance,
including the ability to synchronously burst data at a high
data rate with automatic column-address generation,
the ability to interleave between internal banks in
order to hide precharge time and the capability to randomly
change column addresses on each clock cycle during a burst
access.
8Mx72 Synchronous DRAM
FEATURES
High Frequency = 133MHz
Package:
219 Plastic Ball Grid Array (PBGA), 32 x 25mm
Single 3.3V ±0.3V power supply
Fully Synchronous; all signals registered on positive edge
of system clock cycle
Internal pipelined operation; column address can be changed
every clock cycle
Internal banks for hiding row access/precharge
Programmable Burst length 1,2,4,8 or full page
4096 refresh cycles
Commercial Temperature Range
Organized as 8M x 72
Weight: WEDPN8M72V-133BC - 2.5 grams typical
BENEFITS
40% SPACE SAVINGS
Reduced part count
Reduced I/O count
19% I/O Reduction
Lower inductance and capacitance for low noise
performance
Upgradeable to 16M x 72 density (contact factory for
information)
* This data sheet describes a product subject to change without notice.
32
25
Discrete Approach
S
A
V
I
N
G
S
Area
5 x 265mm2=1328mm2
800mm2
40%
5 x 54 pins = 270 pins
219 Balls
19%
ACTUAL SIZE
22.3
11.9
I/O
Count
11.9
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| WEDPN8M72VR-XBX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Registered SDRAM MCP |
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| WEDPN8M72V-XBX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM MCP |
| WEDPNF8M721V-1010BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1010BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
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