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參數(shù)資料
| 型號： | WEDPN8M72V-125BI |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 8M X 72 SYNCHRONOUS DRAM MODULE, 6 ns, PBGA219 |
| 封裝： | 32 X 25 MM, PLASTIC, BGA-219 |
| 文件頁數(shù)： | 12/15頁 |
| 文件大?。?/td> | 188K |
| 代理商： | WEDPN8M72V-125BI |
6
White Electronic Designs Corporation Phoenix AZ (602) 437-1520
WEDPN8M72V-XBX
The CAS latency is the delay, in clock cycles, between the
registration of a READ command and the availability of the
first piece of output data. The latency can be set to two or
three clocks.
If a READ command is registered at clock edge
n, and the
latency is
m clocks, the data will be available by clock edge
n+m. The I/Os will start driving as a result of the clock edge
one cycle earlier (
n + m - 1), and provided that the relevant
access times are met, the data will be valid by clock edge
n
+ m. For example, assuming that the clock cycle time is such
that all relevant access times are met, if a READ command is
registered at T0 and the latency is programmed to two clocks,
the I/Os will start driving after T1 and the data will be valid by
T2. Table 2 below indicates the operating frequencies at
which each CAS latency setting can be used.
Reserved states should not be used as unknown opera-
tion or incompatibility with future versions may result.
FIG. 4 CAS LATENCY
The normal operating mode is selected by setting M7and
M8 to zero; the other combinations of values for M7 and
M8 are reserved for future use and/or test modes. The pro-
grammed burst length applies to both READ and WRITE
bursts.
Test modes and reserved states should not be used be-
cause unknown operation or incompatibility with future
versions may result.
When M9 = 0, the burst length programmed via M0-M2
applies to both READ and WRITE bursts; when M9 = 1, the
programmed burst length applies to READ bursts, but write
accesses are single-location (nonburst) accesses.
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by
the burst length, the burst type and the star ting column
address, as shown in Table 1.
BURST TYPE
CAS LATENCY
OPERATING MODE
WRITE BURST MODE
TABLE 2 - CAS LATENCY
ALLOWABLE OPERATING
FREQUENCY (MHZ)
CAS
SPEED
LATENCY = 2
LATENCY = 3
-100
≤ 75
≤ 100
-125
≤ 100
≤ 125
CLK
Command
I/O
CLK
Command
I/O
T0
T1
T2
T3
T0
T1
T2
T3
T4
READ
NOP
CAS Latency = 2
DOUT
tLZ
tOH
tAC
READ
NOP
DOUT
tLZ
tOH
tAC
CAS Latency = 3
DON’T CARE
UNDEFINED
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| WEDPN8M72V-125BM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 SDRAM Module |
| WEDPN8M72V-133B2C | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM |
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| WEDPN8M72V-133B2M | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM |
| WEDPN8M72V-133BC | 制造商:Microsemi Corporation 功能描述:8M X 72 SDRAM MODULE, 3.3V, 133 MHZ, 219 PBGA 25MM X 35MM, C - Bulk |
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