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參數(shù)資料
| 型號： | WEDPN16M64V-133B2M |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 16M X 64 SYNCHRONOUS DRAM, 5.5 ns, PBGA219 |
| 封裝： | 21 X 21 MM, PLASTIC, BGA-219 |
| 文件頁數(shù)： | 15/15頁 |
| 文件大?。?/td> | 643K |
| 代理商： | WEDPN16M64V-133B2M |
9
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
WEDPN16M64V-XB2X
January 2005
Rev. 1
(CBR) REFRESH in conventional DRAMs. This command
is nonpersistent, so it must be issued each time a refresh
is required. All active banks must be precharged prior
to issuing an AUTO REFRESH command. The AUTO
REFRESH command should not be issued until the
minimum tRP has been met after the PRECHARGE
command as shown in the operations section.
The addressing is generated by the internal refresh
controller. This makes the address bits “Don’t Care”
during an AUTO REFRESH command. Each 256Mb
SDRAM requires 8,192 AUTO REFRESH cycles
every refresh period (tREF). Providing a distributed
AUTO REFRESH command will meet the refresh
requirement and ensure that each row is refreshed.
Alternatively, 8,192 AUTO REFRESH commands can be
issued in a burst at the minimum cycle rate (tRC), once
every refresh period (tREF).
SELF REFRESH*
The SELF REFRESH command can be used to retain data
in the SDRAM, even if the rest of the system is powered
down. When in the self refresh mode, the SDRAM retains
data without external clocking. The SELF REFRESH
command is initiated like an AUTO REFRESH command
except CKE is disabled (LOW). Once the SELF REFRESH
command is registered, all the inputs to the SDRAM
become “Don’t Care,” with the exception of CKE, which
must remain LOW.
Once self refresh mode is engaged, the SDRAM provides
its own internal clocking, causing it to perform its own
AUTO REFRESH cycles. The SDRAM must remain in
self refresh mode for a minimum period equal to tRAS and
may remain in self refresh mode for an indenite period
beyond that.
The procedure for exiting self refresh requires a sequence
of commands. First, CLK must be stable (stable clock
is dened as a signal cycling within timing constraints
specified for the clock pin) prior to CKE going back
HIGH. Once CKE is HIGH, the SDRAM must have NOP
commands issued (a minimum of two clocks) for tXSR,
because time is required for the completion of any internal
refresh in progress.
Upon exiting the self refresh mode, AUTO REFRESH
commands must be issued as both SELF REFRESH and
AUTO REFRESH utilize the row refresh counter.
* Self refresh available in commercial and industrial temperatures only.
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