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參數(shù)資料
| 型號(hào)： | WED7P064ATA8003C25 |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | PROM |
| 英文描述： | 4M X 16 FLASH 3V PROM CARD, 300 ns, UUC68 |
| 封裝： | CARD-68 |
| 文件頁(yè)數(shù)： | 7/10頁(yè) |
| 文件大?。?/td> | 222K |
| 代理商： | WED7P064ATA8003C25 |
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White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED7PxxxATA80xxC25
July 2005
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specications without notice.
AC CHARACTERISTICS (cont'd):
I/O Input (Read) Timing Specication
Item
Symbol
IEEE Symbol
Min ns.
Max ns.
Data Delay after IORD
td(IORD)
tIGLQV
100
Data Hold following IORD
th(IORD)
tIGHQX
0
IORD Width Time
tw(IORD)
tIGLIGH
165
Address Setup before IORD
tsuA(IORD)
tAVIGL
70
Address Hold following IORD
thA(IORD)
tIGHAX
20
CE Setup before IORD
tsuCE(IORD)
tELIGL
5
CE Hold following IORD
thCE(IORD)
tIGHEH
20
REG Setup before IORD
tsuREG(IORD)
tRGLIGL
5
REG Hold following IORD
thREG(IORD)
tIGHRGH
0
INPACK Delay Falling from IORD
tdfINPACK(IORD)
tIGLIAL
045
INPACK Delay Rising from IORD
tdrINPACK(IORD)
tIGHIAH
45
IOIS16 Delay Falling from Address
tdfIOIS16(ADR)
tAVISL
35
IOIS16 Delay Rising from Address
tdrIOIS16(ADR)
tAVISH
35
Wait Delay Falling from IORD
tdWT(IORD)
tIGLWTL
35
Data Delay from Wait Rising
td(WT)
tWTHQV
0
Wait Width Time
tw(WT)
tWTLWTH
350 (3000 for CF+)
Note: Maximum load on WAIT#, INPACK# and I0IS16# is 1 LSTTL with 50pF total load. All times are in nanoseconds. Minimum time from WAIT# high to IORD# high is Onsec, but
minimum IORD# width must still be met. Wait Width time meets PCMCIA specication of 12ps but is intentionally less in this spec.
I/O Output (Write) Timing Specication
Item
Symbol
IEEE Symbol
Min ns.
Max ns.
Data Setup before IOWR
tsu(IOWR)
tDVIWH
60
Data Hold following IOWR
th(IOWR)
tIWHDX
30
IOWR Width Time
tw(IOWR)
tIWLIWH
165
Address Setup before IOWR
tsuA(IOWR)
tAVIWL
70
Address Hold following IOWR
thA(IOWR)
tIWHAX
20
CE Setup before IOWR
tsuCE(IOWR)
tELIWL
5
CE Hold following IOWR
thCE(IOWR)
tIWHEH
20
REG Setup before IOWR
tsuREG(IOWR)
tRGLIWL
5
REG Hold following IOWR
thREG(IOWR)
tIWHRGH
0
IOIS16 Delay Falling from Address
tdfIOIS16(ADR)
tAVISL
35
IOIS16 Delay Rising from Address
tdrIOIS16(ADR)
tAVISH
35
Wait Delay Falling from IOWR
tdWT(IOWR)
tIWLWTL
35
IOWR high from Wait high
tdrIOWR(WT)
tWTJIWH
0
Wait Width Time
tw(WT)
tWTLWTH
350 (3000for CF+)
Note: The maximum load on WAIT#, INPACK#, and I0IS16# is 1 LSTTL with 50pF total load. All times are in nanoseconds. Minimum time from WAIT# high to IOWR# high is Onsec,
but minimum IOWR# width must still be met. The Wait Width time meets the PCMCIA specication of 12ps but is intentionally less in this specication.
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| WED7P064ATA8004C25 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:32MB to 4GB Flash Card |
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