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參數(shù)資料
| 型號： | WED3EG6418S262D3 |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 16M X 64 DDR DRAM MODULE, DMA184 |
| 封裝： | DIMM-184 |
| 文件頁數(shù)： | 5/6頁 |
| 文件大?。?/td> | 458K |
| 代理商： | WED3EG6418S262D3 |
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED3EG6418S-D3
Sept. 2002
Rev. # 0
*ADVANCED
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
IDD SPECIFICATIONS AND TEST CONDITIONS
(Recommended operating conditions, tA = 0 to 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V)
* Module IDD was calculated on the basis of component IDD and can be different measured according to DQ loading cap.
Parameter
Symbol Conditions
DDR266@CL=2
Max
DDR266@CL=2.5
Max
DDR200@CL=2
Max
Units
Operating Current
IDD0
One device bank; Active = Precharge;
tRC=tRC(MIN); tCK=tCK
(MIN); DQ, DM and DQS inputs changing
once per clock cycle; Address and control
inputs changing once every two cycles.
880
760
mA
Operating Current
IDD1
One device banks; Active-Read-Precharge;
Burst = 2; tRC=tRC(MIN); tCK=tCK
(MIN); lOUT=0mA; Address and control inputs
changing once per clock cycle.
1120
1000
mA
Precharge Power-
Down Standby Current
IDD2P
All device bank idle; Power-down mode;
tCK=tCK(MIN); CKE=(low)
32
mA
Idle Standby Current
IDD2F
CS# = High; All device banks idle;
tCK=tCK(MIN); CKE = high; Address and other
control inputs changing once per clock cycle.
VIN = VREF for DQ, DQS and DM.
256
200
mA
Active Power-Down
Standby Current
IDD3P
One device bank active; Power-down mode;
tCK(MIN); CKE=(low)
320
240
mA
Active Standby Current
IDD3N
CS# = High; CKE = High; One device
bank; Active-Precharge; tRC=tRAS(MAX);
tCK=tCK(MIN); DQ, DM and DQS inputs
changing twice per clock cycle; Address and
other control inputs changing once per clock
cycle
440
mA
Operating Current
IDD4R
Burst = 2; Reads; Continous burst; Once
device bank active; Address and control
inputs changing once per clock cycle;
tCK=tCK(MIN); IOUT=0mA
1280
1240
mA
Operating Current
IDD4W
Burst=2; Writes; Continous burst; Once
device bank active; Address and control
inputs changing once per clock cycle;
tCK=tCK(MIN); DQ,DM and DQS inputs
changing twice per clock cycle.
1280
1240
mA
Auto Refresh Current
IDD5
tRC=tRC(MIN)
1680
1600
mA
Self Refresh Current
IDD6
CKE < 0.2V
Standard
16
mA
Low Power
8
mA
Operating Current
IDD7A
Four bank interleaving Reads (BL=4)
with auto precharge with tRC=tRC(MIN);
tCK=tCK(MIN); Address and control input
change only during Active Read or Write
commands.
3200
2800
mA
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