參數(shù)資料
型號(hào)： WED3DL324V8BI
廠商： MICROSEMI CORP-PMG MICROELECTRONICS
元件分類： DRAM
英文描述： 4M X 32 SYNCHRONOUS DRAM MODULE, 6 ns, PBGA119
封裝： 14 X 22 MM, MO-163, BGA-119
文件頁(yè)數(shù)： 1/27頁(yè)
文件大小： 835K
代理商： WED3DL324V8BI
1
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
White Electronic Designs
WED3DL324V
4Mx32 SDRAM
FEATURES
n 53% Space Savings vs. Monolithic Solution
n Reduced System Inductance and Capacitance
n Pinout and Footprint Compatible to SSRAM 119 BGA
n 3.3V Operating Supply Voltage
n Fully Synchronous to Positive Clock Edge
n Clock Frequencies of 133, 125 and 100MHz
n Burst Operation
Sequential or Interleave
Burst Length = Programmable 1, 2, 4, 8 or Full Page
Burst Read and Write
Multiple Burst Read and Single Write
n Data Mask Control Per Byte
n Auto and Self Refresh
n Automatic and Controlled Precharge Commands
n Suspend Mode and Power Down Mode
n 119 Pin BGA, JEDEC MO-163
The WED3DL324V is a 4Mx32 Synchronous DRAM con-
figured as 4x1Mx32. The SDRAM BGA is constructed
with two 4Mx16 SDRAM die mounted on a multi-layer
laminate substrate and packaged in a 119 lead, 14mm
by 22mm, BGA.
The WED3DL324V is available in clock speeds of
133MHz, 125MHz and 100MHz. The range of operating
frequencies, programmable burst lengths and program-
mable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory sys-
tem applications.
The package and design provides performance enhance-
ments via a 50% reduction in capacitance vs. two mono-
lithic devices. The design includes internal ground and
power planes which reduces inductance on the ground
and power pins allowing for improved decoupling and a
reduction in system noise.
FIG. 1 PINOUT (TOP VIEW)
*NOTE:
Pin B3 is designated as NC/A12. This pin is used for future density upgrades as address pin A12.
PIN DESCRIPTION
DESCRIPTION
1
2
3
456
7
AVDDQ
NC
BA0
NC
A10
A7
VDDQ
A
B
NC
NC/A12*
CAS
A11
NC
B
CNC
NC
BA1
VDD
A9
A8
NC
C
DDQC
NC
VSS
NC
VSS
NC
DQB
D
EDQC
DQC
VSS
CE
VSS
DQB
E
FVDDQ
DQC
VSS
RAS
VSS
DQB
VDDQ
F
GDQC
DQC
DQMC
NC
DQMB
DQB
G
HDQC
DQC
VSS
CKE
VSS
DQB
H
JVDDQ
VDD
NC
VDD
NC
VDD
VDDQ
J
KDQD
DQD
VSS
CLK
VSS
DQA
K
LDQD
DQD
DQMD
NC
DQMA
DQA
L
MVDDQ
DQD
VSS
WE
VSS
DQA
VDDQ
M
NDQD
DQD
VSS
A1
VSS
DQA
N
PDQD
NC
VSS
A0
VSS
NC
DQA
P
RNC
A6
NC
VDD
NC
A2
NC
R
TNC
NC
A5
A4
A3
NC
T
UVDDQ
NC
VDDQ
U
1
2
3
456
7
A0 A11
Address Bus
BA0-1
Bank Select Addresses
DQ
Data Bus
CLK
Clock
CKE
Clock Enable
DQM
Data Input/Output Mask
RAS
Row Address Strobe
CAS
Column Address Strobe
CE
Chip Enable
VDD
Power Supply pins, 3.3V
VDDQ
Data Bus Power Supply pins,3.3V
VSS
Ground pins
Oct. 2001 Rev.1
ECO #15407
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