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參數(shù)資料
| 型號： | WED3DG644V75D1-S |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 4M X 64 SYNCHRONOUS DRAM MODULE, ZMA144 |
| 封裝： | SODIMM-144 |
| 文件頁數(shù)： | 5/9頁 |
| 文件大?。?/td> | 199K |
| 代理商： | WED3DG644V75D1-S |
WED3DG644V-D1
White Electronic Designs
5
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
September 2007
Rev. 5
AC OPERATING TEST CONDITIONS
VCC = 3.3V ± 0.3V, 0 ≤ TA ≤ 70°C
Parameter
Value
Unit
AC input levels (VIH/VIL)
2.4/0.4
V
Input timing measurement reference level
1.4
V
Input rise and fall time
tR/tF = 1/1
ns
Output timing measurement reference level
1.4
V
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Symbol
Version
Unit
Note
7.5, 10
Row active to row active delay
tRRD (min)
15
ns
1
RAS# to CAS# delay
tRCD (min)
20
ns
1
Row precharge time
tRP (min)
20
ns
1
Row active time
tRAS (min)
45
ns
1
tRAS (max)
100
us
Row cycle time
tRC (min)
65
ns
1
Last data in to row precharge
tRDL (min)
2
CLK
2
Last data in to Active delay
tDAL (min)
2 CLK + tRP
—
Last data in to new col. address delay
tCDL (min)
1
CLK
2
Last data in to burst stop
tBDL (min)
1
CLK
2
Col. address to col. address delay
tCCD (min)
1
CLK
3
Number of valid output data
CAS latency=3
2
ea
4
CAS latency=2
1
Notes :
1.
The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer.
2.
Minimum delay is required to complete write.
3.
All parts allow every cycle column address change.
4.
In case of row precharge interrupt, auto precharge and read burst stop.
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