- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄202126 > WED2ZL362MSJ38BC (WHITE ELECTRONIC DESIGNS CORP) 2M X 36 MULTI DEVICE SRAM MODULE, 3.8 ns, PBGA119 PDF資料下載
參數(shù)資料
| 型號(hào)： | WED2ZL362MSJ38BC |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | SRAM |
| 英文描述： | 2M X 36 MULTI DEVICE SRAM MODULE, 3.8 ns, PBGA119 |
| 封裝： | PLASTIC, BGA-119 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 270K |
| 代理商： | WED2ZL362MSJ38BC |
2
White Electronic Designs Corporation Westborough, MA (508) 366-5151
White Electronic Designs
WED2ZL362MSJ
BURST SEQUENCE TABLE
NOTE 1: LBO pin must be tied to High or Low, and Floating State must not be allowed.
Write operation occurs when WE is driven low at the ris-
ing edge of the clock. BW[d:a] can be used for byte write
operation. The pipe-lined NBL SSRAM uses a late-late
write cycle to utilize 100% of the bandwidth. At the first
rising edge of the clock, WE and address are registered,
and the data associated with that address is required two
cycle later.
Subsequent addresses are generated by ADV High for
the burst access as shown below. The starting point of
the burst seguence is provided by the external address.
The burst address counter wraps around to its initial state
upon completion. The burst sequence is determined by
the state of the LBO pin. When this pin is low, linear burst
sequence is selected. And when this pin is high, Inter-
leaved burst sequence is selected.
During normal operation, ZZ must be driven low. When
ZZ is driven high, the SRAM will enter a Power Sleep
Mode after 2 cycles. At this time, internal state of the
SRAM is preserved. When ZZ returns to low, the SRAM
operates after 2 cycles of wake up time.
(Interleaved Burst, LBO = High)
Case 1
Case 2
Case 3
Case 4
LBO Pin
High
A1
A0
A1
A0
A1
A0
A1
A0
First Address
00
0110
11
01
0011
10
1100
01
Fourth Address
1
1001
00
(Linear Burst, LBO = Low)
Case 1
Case 2
Case 3
Case 4
LBO Pin
High
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0001
1011
0110
1100
1011
0001
Fourth Address
1100
0110
FUNCTION DESCRIPTION
The WED2ZL362MSJ is an NBL SSRAM designed to
sustain 100% bus bandwidth by eliminating turnaround
cycle when there is transition from Read to Write, or vice
versa. All inputs (with the exception of OE, LBO and ZZ)
are synchronized to rising clock edges.
All read, write and deselect cycles are initiated by the
ADV input. Subsequent burst addresses can be inter-
nally generated by the burst advance pin (ADV). ADV
should be driven to Low once the device has been dese-
lected in order to load a new address for next operation.
Clock Enable (CKE) pin allows the operation of the chip
to be suspended as long as necessary. When CKE is
high, all synchronous inputs are ignored and the internal
device registers will hold their previous values. NBL
SSRAM latches external address and initiates a cycle
when CKE and ADV are driven low at the rising edge of
the clock.
Output Enable (OE) can be used to disable the output at
any given time. Read operation is initiated when at the
rising edge of the clock, the address presented to the
address inputs are latched in the address register, CKE
is driven low, the write enable input signals WE are driven
high, and ADV driven low. The internal array is read be-
tween the first rising edge and the second rising edge of
the clock and the data is latched in the output register. At
the second clock edge the data is driven out of the SRAM.
During read operation OE must be driven low for the
device to drive out the requested data.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| WMS256K16L-20DLCA | 256K X 16 STANDARD SRAM, 20 ns, CDSO44 |
| WS128K32-55G2LQ | 128K X 32 MULTI DEVICE SRAM MODULE, 55 ns, CQFP68 |
| W3EG7266S202D3 | 64M X 72 DDR DRAM MODULE, 0.75 ns, DMA184 |
| W19B320ABBBG | 2M X 16 FLASH 3V PROM, 70 ns, PBGA48 |
| W25X20-VSSI-G | 2M X 1 FLASH 2.7V PROM, PDSO8 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WED2ZL64512S | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512K x 64 Synchronous Pipeline NBL SRAM |
| WED2ZL64512S35BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512K x 64 Synchronous Pipeline NBL SRAM |
| WED2ZL64512S38BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512K x 64 Synchronous Pipeline NBL SRAM |
| WED2ZL64512S42BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512K x 64 Synchronous Pipeline NBL SRAM |
| WED2ZL64512S50BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512K x 64 Synchronous Pipeline NBL SRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。