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參數(shù)資料
| 型號： | WED2ZL361MV42BC |
| 元件分類： | SRAM |
| 英文描述： | 1M X 36 ZBT SRAM, 4.2 ns, PBGA119 |
| 封裝： | BGA-119 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大?。?/td> | 213K |
| 代理商： | WED2ZL361MV42BC |
1
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
WED2ZL361MV
September 2000 Rev. 0
ECO #13181
DESCRIPTION
The WEDC SyncBurst - SRAM family employs high-speed, low-
power CMOS designs that are fabricated using an advanced CMOS
process. WEDC’s 32Mb SyncBurst SRAMs integrate two 1M x 18
SRAMs into a single BGA package to provide 1M x 36 configuration.
All synchronous inputs pass through registers controlled by a
positive-edge-triggered single-clock input (CLK). The NBL or No
Bus Latency Memory utilizes all the bandwidth in any combination
of operating cycles. Address, data inputs, and all control signals
except output enable and linear burst order are synchronized to input
clock. Burst order control must be tied “High or Low.” Asynchro-
nous inputs include the sleep mode enable (ZZ). Output Enable
controls the outputs at any given time. Write cycles are internally
self-timed and initiated by the rising edge of the clock input. This
feature eliminates complex off-chip write pulse generation and
provides increased timing flexibility for incoming signals.
* This data sheet describes a product under development, not fully
characterized, and is subject to change without notice.
1M x 36 Synchronous Pipeline Burst NBL SRAM PRELIMINARY*
FIG. 1
BLOCK DIAGRAM
PIN CONFIGURATION
(TOP VIEW)
Address Bus
(SA0 – SA19)
DQa, DQb
DQPa, DQPb
DQc, DQd
DQPc, DQPd
DQa – DQd
DQPa – DQPd
1M x 18
CLK
CKE
ADV
LBO
CS1
CS2
OE
WE
ZZ
CLK
CKE
ADV
LBO
CE1
CE2
OE
WE
ZZ
CLK
CKE
ADV
LBO
CS1
CS2
OE
WE
ZZ
BWd
BWa
BWc
BWb
FEATURES
s Fast clock speed: 166, 150, 133, and 100MHz
s Fast access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns
s Fast OE access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns
s Single +3.3V
± 5% power supply (VDD)
s Snooze Mode for reduced-standby power
s Individual Byte Write control
s Clock-controlled and registered addresses, data I/Os and
control signals
s Burst control (interleaved or linear burst)
s Packaging:
119-bump BGA package
s Low capacitive bus loading
123
4
5
67
A
VDD
SA
VDD
B
SA
CE2
SA
ADV
SA
CE2
NC
C
NC
SA
VDD
SA
NC
D
DQc
DQPc
VSS
NC
VSS
DQPb
DQb
E
DQc
VSS
CE1
VSS
DQb
F
VDD
DQc
VSS
OE
VSS
DQb
VDD
G
DQc
BWc
SA
BWb
DQb
H
DQc
VSS
WE
VSS
DQb
J
VDD
NC
VDD
NC
VDD
K
DQd
VSS
CLK
VSS
DQa
L
DQd
BWd
NC
BWa
DQa
M
VDD
DQd
VSS
CKE
VSS
DQa
VDD
N
DQd
VSS
SA1
VSS
DQa
P
DQd
DQPd
VSS
SA0
VSS
DQPa
DQa
R
NC
SA
LBO
VDD
NC
SA
NC
T
NC
SA
NC
ZZ
U
VDD
NC
VDD
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WED2ZL361MV42BI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1Mx36 Synchronous Pipeline Burst NBL SRAM |
| WED2ZL361MV50BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1Mx36 Synchronous Pipeline Burst NBL SRAM |
| WED2ZL361MV50BI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1Mx36 Synchronous Pipeline Burst NBL SRAM |
| WED2ZL361MV-BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NBL SSRAM MCP |
| WED2ZL362MS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NBL SSRAM MCP |
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