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參數(shù)資料
| 型號(hào)： | WED2DL36513V38BC |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | SRAM |
| 英文描述： | 512K X 36 MULTI DEVICE SRAM MODULE, 3.8 ns, PBGA119 |
| 封裝： | PLASTIC, BGA-119 |
| 文件頁(yè)數(shù)： | 1/10頁(yè) |
| 文件大?。?/td> | 203K |
| 代理商： | WED2DL36513V38BC |
1
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
White Electronic Designs
WED2DL36513V
July 2002 Rev. 3
ECO #14637
DESCRIPTION
The WEDC SyncBurst - SRAM family employs high-
speed, low-power CMOS designs that are fabricated
using an advanced CMOS process. WEDCs 16Mb
SyncBurst SRAMs integrate two 512K x 18 SRAMs into
a single BGA package to provide 512K x 36 configura-
tion. All synchronous inputs pass through registers con-
trolled by a positive-edge-triggered single-clock input
(CLK). The synchronous inputs include all addresses, all
data inputs, active LOW chip enable (CE), burst control
inputs (ADSC, ADSP, ADV), byte write enables (BW0-3)
and global write (GW). Asynchronous inputs include the
output enable (OE), clock (CLK) and snooze enable (ZZ).
There is also a burst mode input (MODE) that selects
between interleaved and linear burst modes. Write Cycles
can be from one to four bytes wide, as controlled by the
write control inputs. Burst operation can be initiated with
either address status processor (ADSP) or address sta-
tus controller (ADSC) inputs. Subsequent burst ad-
dresses can be internally generated as controlled by the
burst advance input (ADV).
* This data sheet describes a product under development, not fully
characterized, and is subject to change without notice.
512Kx36 Synchronous Pipeline Burst SRAM
FEATURES
■ Fast clock speed: 200, 166, 150 & 133MHz
■ Fast access times: 2.5ns, 3.5ns, 3.8ns & 4.0ns
■ Fast OE access times: 2.5ns, 3.5ns, 3.8ns 4.0ns
■ Available with 1.5ns setup and 0.5ns hold times or
1.0ns setup and hold times.
■ Single +3.3V power supply (VDD)
■ Seperate +3.3V or +2.5V isolated output buffer
supply (VDDQ)
■ Snooze Mode for reduced-power standby
■ Single-cycle deselect
■ Common data inputs and data outputs
■ Individual Byte Write control and Global Write
■ Clock-controlled and registered addresses, data
I/Os and control signals
■ Burst control (interleaved or linear burst)
■ Packaging:
119-bump BGA package
■ Low capacitive bus loading
■ IEEE 1149.1 JTAG Compatible Boundary Scan
FIG. 1
BLOCK DIAGRAM
PIN CONFIGURATION
(TOP VIEW)
1
2
345
6
7
A
VDDQ
SA
ADSP
SA
VDDQ
B
NC
SA
ADSC
SA
NC
C
NC
SA
VDD
SA
NC
D
DQc
DQPc
VSS
NC
VSS
DQPb
DQb
E
DQc
VSS
CE
VSS
DQb
F
VDDQ
DQc
VSS
OE
VSS
DQb
VDDQ
G
DQc
BWc
ADV
BWb
DQb
H
DQc
VSS
GW
VSS
DQb
J
VDDQ
VDD
NC
VDD
NC
VDD
VDDQ
K
DQd
VSS
CLK
VSS
DQa
L
DQd
BWd
NC
BWa
DQa
M
VDDQ
DQd
VSS
BWE
VSS
DQa
VDDQ
N
DQd
VSS
SA1
VSS
DQa
P
DQd
DQPd
VSS
SA0
VSS
DQPa
DQa
R
NC
SA
MODE
VDD
NC
SA
NC
T
NC
SA
NC
ZZ
U
VDDQ
TMD
TDI
TCK
TDO
NC
VDDQ
DQb, DQPb
DQa, DQPa
GW
ADV
SA
CLK
ADSP
ADSC
OE
BWE
CE
MODE
ZZ
BWa
BWb
512K x 18
SSRAM
DQd, DQPd
DQc, DQPc
512K x 18
SSRAM
BWc
BWd
* Enable on pins C7 and R7 are options for the three CE density only.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WED2DL36513V-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SSRAM MCP |
| WED2EG472512V5D2 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:16MB (4x512Kx72) SYNC BURST PIPELINE, DUAL KEY DIMM |
| WED2EG472512V65D2 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:16MB (4x512Kx72) SYNC BURST PIPELINE, DUAL KEY DIMM |
| WED2EG472512V6D2 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:16MB (4x512Kx72) SYNC BURST PIPELINE, DUAL KEY DIMM |
| WED2EG472512V7D2 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:16MB (4x512Kx72) SYNC BURST PIPELINE, DUAL KEY DIMM |
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