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參數(shù)資料
| 型號(hào)： | WED2DG472512V65D2 |
| 元件分類： | SRAM |
| 英文描述： | 2M X 72 MULTI DEVICE SRAM MODULE, 3.7 ns, DMA168 |
| 封裝： | DIMM-168 |
| 文件頁(yè)數(shù)： | 3/9頁(yè) |
| 文件大?。?/td> | 190K |
| 代理商： | WED2DG472512V65D2 |
3
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
WED2DG472512V-D2
SYNC BURST – TRUTH TABLE
1234567890123
Operation
E1
E2
E3
E4
ADSP
ADSC
ADV
GW
G
CLK
DQ
Addr. Used
Deselected Cycle, Power Down; Bank 1
H
X
L
X
L-H
High-Z
None
Deselected Cycle, Power Down; Bank 2
X
H
X
L
X
L-H
High-Z
None
Read Cycle, Begin Burst; Bank 1
L
H
L
X
L
L-H
Q
External
Read Cycle, Begin Burst; Bank 1
L
H
L
X
H
L-H
High-Z
External
Read Cycle, Begin Burst, Bank 2
H
L
X
L
L-H
Q
External
Read Cycle, Begin Burst; Bank 2
H
L
X
H
L-H
High-Z
External
Write Cycle, Begin Burst; Bank 1
L
H
L
X
L
X
L-H
D
External
Write Cycle, Begin Burst; Bank 2
H
L
H
L
X
L
X
L-H
D
External
Read Cycle, Begin Burst; Bank 1
L
H
L
X
H
L
L-H
Q
External
Read Cycle, Begin Burst; Bank 1
L
H
L
X
H
L-H
High-Z
External
Read Cycle, Begin Burst; Bank 2
H
L
H
L
X
H
L
L-H
Q
External
Read Cycle, Begin Burst; Bank 2
H
L
H
L
X
H
L-H
High-Z
External
Read Cycle, Continue Burst; Bank 1
X
H
X
H
L
H
L
L-H
Q
Next
Read Cycle, Continue Burst; Bank 1
X
H
X
H
L
H
L-H
High-Z
Next
Read Cycle, Continue Burst; Bank 2
H
X
H
L
H
L
L-H
Q
Next
Read Cycle, Continue Burst; Bank 2
H
X
H
L
H
L-H
High-Z
Next
Read Cycle, Continue Burst; Bank 1
H
X
H
L
H
L
L-H
Q
Next
Read Cycle, Continue Burst; Bank 1
H
X
H
L
H
L-H
High-Z
Next
Read Cycle, Continue Burst; Bank 2
H
X
H
L
H
L
L-H
Q
Next
Read Cycle, Continue Burst; Bank 2
H
X
H
L
H
L-H
High-Z
Next
Write Cycle, Continue Burst; Bank 1
X
H
L
X
L-H
D
Next
Write Cycle, Continue Burst; Bank 1
H
X
H
L
X
L-H
D
Next
Write Cycle, Continue Burst; Bank 2
H
X
H
L
X
L-H
D
Next
Write Cycle, Continue Burst; Bank 2
H
X
H
L
X
L-H
D
Next
Read Cycle, Suspend Burst; Bank 1
X
H
L
L-H
Q
Current
Read Cycle, Suspend Burst; Bank 1
X
H
L-H
High-Z
Current
Read Cycle, Suspend Burst; Bank 2
H
X
H
L
L-H
Q
Current
Read Cycle, Suspend Burst; Bank 2
H
X
H
L-H
High-Z
Current
Read Cycle, Suspend Burst; Bank 1
H
X
H
L
L-H
Q
Current
Read Cycle, Suspend Burst; Bank 1
H
X
H
L-H
High-Z
Current
Read Cycle, Suspend Burst; Bank 2
H
X
H
L
L-H
Q
Current
Read Cycle, Suspend Burst; Bank 2
H
X
H
L-H
High-Z
Current
Write Cycle, Suspend Burst; Bank 1
X
H
L
X
L-H
D
Current
Write Cycle, Suspend Burst; Bank 1
H
X
H
L
X
L-H
D
Current
Write Cycle, Suspend Burst; Bank 2
H
X
H
L
X
L-H
D
Current
Write Cycle, Suspend Burst; Bank 2
H
X
H
L
X
L-H
D
Current
Note
A
Note A: All truth Table Functions Repeat for Bank 3 (E3) and Bank 4 (E4).
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| WED2DG472512V-D2 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:16MB (4x512Kx72) SYNC BURST-PIPELINE, DUAL KEY DIMM |
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