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參數(shù)資料
| 型號(hào)： | WE128K32N-200G2TMA |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | PROM |
| 英文描述： | 128K X 32 EEPROM 5V MODULE, 125 ns, CQFP68 |
| 封裝： | 22.40 X 22.40 MM, 4.57 MM HEIGHT, CERAMIC, QFP-68 |
| 文件頁(yè)數(shù)： | 13/14頁(yè) |
| 文件大?。?/td> | 496K |
| 代理商： | WE128K32N-200G2TMA |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)當(dāng)前第13頁(yè)第14頁(yè)
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White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
WE128K32-XXX
March 2008
Rev. 12
White Electronic Designs Corp. reserves the right to change products or specications without notice.
PAGE WRITE OPERATION
The WE128K32-XXX has a page write operation that
allows one to 128 bytes of data to be written into the device
and consecutively loads during the internal programming
period. Successive bytes may be loaded in the same
manner after the rst data byte has been loaded. An
internal timer begins a time out operation at each write
cycle. If another write cycle is completed within 150μs
or less, a new time out period begins. Each write cycle
restarts the delay period. The write cycles can be continued
as long as the interval is less than the time out period.
The usual procedure is to increment the least signicant
address lines from A0 through A6 at each write cycle. In
this manner a page of up to 128 bytes can be loaded in
to the EEPROM in a burst mode before beginning the
relatively long interval programming cycle.
After the 150μs time out is completed, the EEPROM
begins an internal write cycle. During this cycle the entire
page of bytes will be written at the same time. The internal
programming cycle is the same regardless of the number
of bytes accessed.
FIGURE 9 – PAGE MODE WRITE WAVEFORMS
PAGE WRITE CHARACTERISTICS
(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
Page Mode Write Characteristics
Symbol
Unit
Parameter
Min
Max
Write Cycle Time, TYP = 6ms
tWC
10
ms
Address Set-up Time
tAS
0ns
Address Hold Time (1)
tAH
100
ns
Data Set-up Time
tDS
50
ns
Data Hold Time
tDH
10
ns
Write Pulse Width
tWP
100
ns
Byte Load Cycle Time
tBLC
150
μs
Write Pulse Width High
tWPH
50
ns
1. Page address must remain valid for duration of write cycle.
OE#
CS#
WE#
ADDRESS
DATA
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