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參數(shù)資料
| 型號(hào)： | WE128K32N-125H1C |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | PROM |
| 英文描述： | 128K X 32 EEPROM 5V MODULE, 125 ns, CPGA66 |
| 封裝： | 1.075 X 1.075 INCH, HERMETIC SEALED, CERAMIC, HIP-66 |
| 文件頁(yè)數(shù)： | 11/14頁(yè) |
| 文件大?。?/td> | 496K |
| 代理商： | WE128K32N-125H1C |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)當(dāng)前第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)
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White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
WE128K32-XXX
March 2008
Rev. 12
White Electronic Designs Corp. reserves the right to change products or specications without notice.
READ
The WE128K32-XXX stores data at the memory location
determined by the address pins. When CS# and OE# are
low and WE# is high, this data is present on the outputs.
When CS# and OE# are high, the outputs are in a high
impedance state. This two line control prevents bus
contention.
Notes:
OE# may be delayed up to tACS - tOE after the falling edge of CS# without impact
on tOE or by tACC - tOE after an address change without impact on tACC.
AC READ CHARACTERISTICS
VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C*
Read Cycle Parameter
Symbol
-125
-140
-150
-200
-250
-300
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Read Cycle Time
tRC
125
140
150
200
250
300
ns
Address Access Time
tACC
125
140
150
200
250
300
ns
Chip Select Access Time
tACS
125
140
150
200
250
300
ns
Output Hold from Add. Change, OE#
or CS#
tOH
000000
ns
Output Enable to Output Valid
tOE
0
50
0
55
0
55
0
55
0
85
0
85
ns
Chip Select or OE# to High Z
Output
tDF
60
70
ns
FIGURE 7 – READ WAVEFORMS
t
ADDRESS
CS#
OE#
OUTPUT
OH
tDF
tACC
t RC
tOE
tACS
OUTPUT
VALID
ADDRESS VALID
HIGH Z
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