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參數(shù)資料
| 型號： | WE128K32-200G4MA |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | PROM |
| 英文描述： | 128K X 32 EEPROM 5V MODULE, 200 ns, CQMA68 |
| 封裝： | CERAMIC, QFP-68 |
| 文件頁數(shù)： | 12/15頁 |
| 文件大?。?/td> | 297K |
| 代理商： | WE128K32-200G4MA |
6
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WE128K32-XXX
AC READ CHARACTERISTICS
(VCC = 5.0V, VSS = 0V, TA = -55
°C to +125°C)
FIG. 7
READ WAVEFORMS
t
ADDRESS
CS
OE
OUTPUT
OH
tDF
t ACC
t RC
t OE
tACS
OUTPUT
VALID
ADDRESS VALID
HIGH Z
READ
The WE128K32-XXX stores data at the memory location
determined by the address pins. When CS and OE are low and
WE is high, this data is present on the outputs. When CS and
OE are high, the outputs are in a high impedance state. This
two line control prevents bus contention.
NOTES:
OE may be delayed up to tACS - tOE after the
falling edge of CS without impact on tOE or by
tACC - tOE after an address change without
impact on tACC.
Read Cycle Parameter
Symbol
-120
-140
-150
-200
-250
-300
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Read Cycle Time
tRC
120
140
150
200
250
300
ns
Address Access Time
tACC
120
140
150
200
250
300
ns
Chip Select Access Time
tACS
120
140
150
200
250
300
ns
Output Hold from Add. Change, OE or CS
tOH
0
00000
ns
Output Enable to Output Valid
tOE
0
50
0
55
0
55
0
55
0
85
0
85
ns
Chip Select or OE to High Z Output
tDF
70
ns
CS1-4
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