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參數(shù)資料
| 型號： | WE128K32-200G2TME |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | PROM |
| 英文描述： | 128K X 32 EEPROM 5V MODULE, 200 ns, CQFP68 |
| 封裝： | 22.40 X 22.40 MM, 4.57 MM HEIGHT, HERMETIC SEALED, CERAMIC, LQFP-68 |
| 文件頁數(shù)： | 9/11頁 |
| 文件大小： | 161K |
| 代理商： | WE128K32-200G2TME |
7
White Electronic Designs Corporation Phoenix, AZ (602) 437-1520
WE128K32-XG2TXE
PAGE WRITE OPERATION
The WE128K32-XG2TXE has a page write operation that allows
one to 128 bytes of data to be written into the device and
consecutively loads during the internal programming period.
Successive bytes may be loaded in the same manner after the first
data byte has been loaded. An internal timer begins a time out
operation at each write cycle. If another write cycle is completed
within 30
s or less, a new time out period begins. Each write
cycle restarts the delay period. The write cycles can be continued
as long as the interval is less than the time out period.
The usual procedure is to increment the least significant
address lines from A0 through A6 at each write cycle. In this
manner a page of up to 128 bytes can be loaded in to the
EEPROM in a burst mode before beginning the relatively long
interval programming cycle.
After the 30
s time out is completed, the EEPROM begins an
internal write cycle. During this cycle the entire page of bytes
will be written at the same time. The internal programming
cycle is the same regardless of the number of bytes accessed.
PAGE WRITE CHARACTERISTICS
(VCC = 5.0V, VSS = 0V, TA = -55
°C to +125°C)
FIG. 7
PAGE WRITE WAVEFORMS
CS CONTROLLED(1)
1. This parameter is guarenteed by design but not tested.
Page Mode Write Characteristics
Parameter
Symbol
Min
Max
Unit
Write Cycle Time, TYP = 6ms
tWC
10
ms
Address Set-up Time
tAS
0ns
Address Hold Time
tAH
150
ns
Data Set-up Time
tDS
100
ns
Data Hold Time
tDH
10
ns
Write Pulse Width
tWP
250
ns
Byte Load Cycle Time (1)
tBLC
30
s
Byte Load Window (1)
tBL
100
s
Data Latch Time
tDL
300
ns
RESET Protect Time (1)
tRP
100
s
RESET High Time (1)
tRES
1
s
DATA IN
tCS
tCH
t OEH
tWP
tOES
tBLC
tAS
tAH
tBL
t WC
tDS
WE
tDL
OE
CS
RESET
Vcc
ADDRESS (2)
A0-16
tRES
tRP
tDH
NOTES:
1. tDF and tDFR are defined as the time at which the outputs achieve the
open circuit conditions and are no longer driven.
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