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參數資料
| 型號： | BU-61865G4-162K |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, MQFP72 |
| 封裝： | GULL WING, PACKAGE-72 |
| 文件頁數： | 41/56頁 |
| 文件大?。?/td> | 321K |
| 代理商： | BU-61865G4-162K |
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46
DESCRIPTION
PROCESSOR INTERFACE CONTROL
SIGNAL NAME
I/O Enable. Tri-state control for external address and data buffers. Generally not used in buffered mode. When low, indi-
cates that the Enhanced Mini-ACE is currently performing a host access to an internal register, or internal or (for trans-
parent mode) external RAM. In transparent mode, IOEN (low) should be used to enable external address and data bus
tri-state buffers.
IOEN(0)
58
PIN
Handshake output to host processor. For a nonzero wait state read access, READYD is asserted at the end of a host
transfer cycle to indicate that data is available to be read on D15 through D0 when asserted (low). For a nonzero wait
state write cycle, READYD is asserted at the end of the cycle to indicate that data has been transferred to a register or
RAM location. For both nonzero wait reads and writes, the host must assert STRBD low until READYD is asserted low.
In the (buffered) zero wait state mode, this output is normally logic "0", indicating that the Enhanced Mini-ACE is in a
state ready to accept a subsequent host transfer cycle. In zero wait mode, READYD will transition from low to high during
(or just after) a host transfer cycle, when the Enhanced Mini-ACE initiates its internal transfer to or from registers or inter-
nal RAM. When the Enhanced Mini-ACE completes its internal transfer, READYD returns to logic "0", indicating it is
ready for the host to initiate a subsequent transfer cycle.
READYD
56
Used to select between the buffered mode (when strapped to logic “0”) and transparent/DMA mode (when strapped to
logic “1") for the host processor interface.
TRANSPARENT /
BUFFERED
55
Memory Enable or Trigger Select input. In 8-bit buffered mode, input signal (TRIG-SEL) used to select the order in which
byte pairs are transferred to or from the Enhanced MINI-ACE by the host processor. In the 8-bit buffered mode,
TRIG_SEL should be asserted high (logic 1) if the byte order for both read operations and write operations is MSB fol-
lowed by LSB. TRIG_SEL should be asserted low (logic 0) if the byte order for both read operations and write opera-
tions is LSB followed by MSB.
This signal has no operation in the 16-bit buffered mode (it does not need to be connected).
In transparent mode, active low input MEMENA_IN, used as a Chip Select (CS) input to the Enhanced Mini-ACE's inter-
nal shared RAM. If only internal RAM is used, should be connected directly to the output of a gate that is OR'ing the
DTACK and IOEN output signals.
Memory/Register. Generally connected to either a CPU address line or address decoder output. Selects between mem-
ory access (MEM/REG = "1") or register access (MEM/REG = "0").
Subsystem Flag (RT) or External Trigger (BC/Word Monitor) input. In RT mode, if this input is asserted low, the
Subsystem Flag bit will be set in the ENHANCED MINI-ACE's RT Status Word. If the SSFLAG input is logic "0" while bit
8 of Configuration Register #1 has been programmed to logic "1" (cleared), the Subsystem Flag RT Status Word bit will
become logic "1," but bit 8 of Configuration Register #1, SUBSYSTEM FLAG, will return logic "1" when read. That is, the
sense on the SSFLAG input has no effect on the SUBSYSTEM FLAG register bit.
In the non-enhanced BC mode, this signal operates as an External Trigger input. In BC mode, if the external BC Start
option is enabled (bit 7 of Configuration Register #1), a low to high transition on this input will issue a BC Start com-
mand, starting execution of the current BC frame.
In the enhanced BC mode, during the execution of a Wait for External Trigger (WTG) instruction, the Enhanced Mini-ACE
BC will wait for a low-to-high transition on EXT_TRIG before proceeding to the next instruction.
In the Word Monitor mode, if the external trigger is enabled (bit 7 of Configuration Register #1), a low to high transition
on this input will initiate a monitor start.
This input has no effect in Message Monitor mode.
TRIG_SEL (1) /
MEMENA_IN (1)
MEM / REG(1)
SSFLAG (1) /
EXT_TRIG(1)
28
1
32
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