參數(shù)資料
型號(hào): BU-61865G4-162K
廠商: DATA DEVICE CORP
元件分類: 微控制器/微處理器
英文描述: 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, MQFP72
封裝: GULL WING, PACKAGE-72
文件頁(yè)數(shù): 39/56頁(yè)
文件大?。?/td> 321K
代理商: BU-61865G4-162K
44
BU-61843(5) /
61743(5)
(4KK RAM)
PROCESSOR ADDRESS BUS (CONTINUED)
DESCRIPTION
A0(LSB)
A6
A1
A7
A2
A8
A3
A9
A4
A10
A5
A11
SIGNAL NAME
A0(LSB)
A6
A1
A7
A2
A8
A3
A9
PIN
A4
A10
15
22
27
11
12
6
Lower 12 bits of 16-bit bi-directional address bus. In both the buffered and transparent modes,
the host CPU accesses the Enhanced Mini-ACE registers and internal RAM by means of A11 -
A0 (4K version). For the 64K versions, A15 - A12 are also used for this purpose.
In buffered mode, A12-A0 (or A15-A0) are inputs only. In the transparent mode, A12-A0 (or
A15-A0) are inputs during CPU accesses and become outputs, driving outward (towards the
CPU) when the 1553 protocol/memory management logic accesses up to 64K words of external
RAM.
In transparent mode, the address bus is driven outward only when the signal DTACK is low
(indicating that the Enhanced Mini-ACE has control of the RAM interface bus) and IOEN is high,
indicating a non-host access. Most of the time, including immediately after power turn-on, A12-
A0 (or A15-A0) will be in high impedance (input) state.
BU-61864(5)
(64K RAM)
10
69
9
4
A5
A11
68
3
相關(guān)PDF資料
PDF描述
BU-61745G4 2 CHANNEL(S), MIL-STD-1553 CONTROLLER, CQFP72
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