參數(shù)資料
型號： WC32P040-XXM
英文描述： 32-Bit, Nonmultiplexed External Address and Data Buses with Synchronous Interface
中文描述： 32位，非復用的外部地址和數(shù)據(jù)總線與同步接口
文件頁數(shù)： 4/23頁
文件大?。?/td> 739K
代理商： WC32P040-XXM
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WC32P040-XXM
July 1998
ADDRESSSING
The WC32P040 supports the basic addressing modes of
the 68000 family. The register indirect addressing modes
support postincrement, predecrement, offset, and indexing.
The program counter indirect mode also has indexing and
offset capabilities.
ADDRESSING MODES
Addressing
Register Direct
Data Register Direct
Address Register Direct
Register Indirect
Address Register Indirect
Address Register Indirect with Postincrement
Address Register Indirect with Predecrement
Address Register Indirect with Displacement
Register Indirect with Index
Address Register Indirect with Index (8-Bit Displacement)
Address Register Indirect with Index (Base Displacement)
Memory Indirect
Memory Indirect Postindexed
Memory Indirect Preindexed
Program Counter Indirect with Displacement
Program Counter Indirect with Index
PC Indirect with Index (8-Bit Displacement)
PC Indirect with Index (Base Displacement)
Program Counter Memory Indirect
PC Memory Indirect Postindexed
PC Memory Indirect Preindexed
Absolute
Absolute Short
Absolute Long
Immediate
Syntax
Dn
An
(An)
(An) +
- (An)
(d16,An)
(d8,An,Xn)
(bd,An,Xn)
([bd,An],Xn,od)
([bd,An,Xn],od)
(d16,PC)
(d8,PC,Xn)
(bd,PC,Xn)
([bd,PC],Xn,od)
([bd,PC,Xn],od)
(xxx).W
(xxx).L
#<xxx>
INSTRUCTION SET SUMMARY
Opcode
ABCD
Operation
BCD Source + BCD Destination + X Destination
Syntax
ABCD Dy,Dx
ABCD -(Ay),-(Ax)
ADD <ea>,Dn
ADD Dn,<ea>
ADDA <ea>,An
ADDI #<data>,<ea>
ADDQ #<data>,<ea>
ADDX Dy,Dx
ADDX -(Ay),-(Ax)
AND <ea>,Dn
AND Dn,<ea>
ANDI #<data>,<ea>
ANDI #<data>,CCR
ANDI #<data>,SR
ADD
Source + Destination Destination
ADDA
ADDI
ADDQ
ADDX
Source + Destination Destination
Immediate Data + Destination Destination
Immediate Data + Destination Destination
Source + Destination + X Destination
AND
Source
Λ
Destination Destination
ANDI
Immediate Data
Λ
Destination Destination
Source
Λ
CCR CCR
If supervisor state
then Source
Λ
SR SR
else TRAP
ANDI to CCR
ANDI to SR
DATA FORMATS
The WC32P040 supports the basic data formats of the
68000 family. Some data formats apply only to the IU,
some only to the FPU, and some to both. In addition, the
instruction set supports operations on other data formats
such as memory addresses.
DATA FORMATS
Operand Data
Format
Bit
1 Bit
Bit Field
1-32 Bits
Binary-Coded
Decimal (BCD)
Byte Integer
8 Bits
IU, FPU
Word Integer
16 Bits
IU, FPU
Long-Word Integer
32 Bits
IU, FPU
Quad-Word Integer
64 Bits
16-Byte
128 Bits
Size
Supported In
Notes
IU
IU
IU
—
Field of Consecutive Bits
Packed: 2 Digits/Byte;
Unpacked: 1 Digit/Byte
—
—
—
Any Two Data Registers
Memory Only, Aligned to
16-Byte Boundary
1-Bit Sign, 8-Bit Exponent,
23-Bit Fraction
1-Bit Sign,11-Bit
Exponent, 52-Bit Fraction
1-Bit Sign,15-Bit
Exponent, 64-Bit Mantissa
8 Bits
IU
IU
Single-Precision Real
32 Bits
FPU
Double-Precision
Real
Extended-Precision
Real
64 Bits
FPU
80 Bits
FPU
相關(guān)PDF資料
PDF描述
WC701 RF Chip Inductor
WC701_1 RF Chip Inductor Catalog - Design Kits. Selection Guide. Perfomance Specs (12/02) - pages 1-5 (5 pages)
WC701_2 RF Chip Inductor Catalog - Series: 0402CD. 0603CD. 0805CD. 0805CM. 0805FT (12/02) - pages 6-15 (10 pages)
WC701_3 WIRE-WOUND RF CHIP INDUCTORS
WC701_4 RF Chip Inductor Catalog - Application Notes. Pulse Contacts (12/02) - pages 26-30 (5 pages)
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