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參數(shù)資料
| 型號： | WB1356X |
| 英文描述： | Serial-Input Frequency Synthesizer |
| 中文描述： | 串行輸入頻率合成器 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大小： | 201K |
| 代理商： | WB1356X |
Dual Serial Input PLL with 2.0- and 1.1-GHz Prescalers
WB1356
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
February 2, 2000, rev. *A
Features
Operating voltage 2.7V to 5.5V
Operating frequency to 2.0 GHz on PLL1 and 1.1 GHz
on PLL2 with prescaler ratios of 64/65 and 128/129
Lock detect feature
Power-down mode ICC < 1 A typical at 3.0V
Serial data input accepts data clock rates as low as
1kHz
Low power/voltage operation with low current standby
mode
On-chip reference oscillator
Available in a 20-pin TSSOP (Thin Shrink Small Outline
Package)
Applications
The Cypress WB1356 is a dual serial input PLL frequency
synthesizer designed for high performance dual conversion
TV, VCR, and Set-top tuner sections, as well as downstream
receivers for cable modems. The WB1356 is also well suited
for high-volume, low-cost wireless communications applica-
tions. One 2.0-GHz and 1.1-GHz prescaler, each with pulse
swallow capability are included. The device operates from
2.7V and dissipates only 33 mW.
Dual PLL Block Diagram
Pin Configuration
VCC2
VP2
DOPLL2
GND
FIN2
FIN2#
GND
LE
DATA
CLOCK
20
19
18
17
16
15
14
13
12
11
VCC1
VP1
DOPLL1
GND
FIN1
FIN1#
GND
OSC_IN
OSC_OUT
FO/LD
1
2
3
4
5
6
7
8
9
10
Binary 7-Bit
Prescaler
Phase
Detector
19-Bit
Pwr-dwn
Swallow Counter
Binary 11-Bit
Programmable Counter
64/65 or
Latch
PLL1
20-Bit Latch
Prescaler
64/65 or
Cntrl 22-Bit
Shift
Reg.
Binary 7-Bit
Swallow Counter
Binary 11-Bit
Programmable Counter
19-Bit
Pwr-dwn
Latch
PLL2
15-Bit
Reference Counter
15-Bit
Reference Counter
Phase
Detector
Charge
Pump
fr fp
Monitor
Output
Charge
Pump
Power
Control
Selector
GND
VP2
GND
VCC
FIN1
FIN1#
OSC_IN
LE
DATA
CLOCK
FIN2
FIN2#
VP1
DOPLL1
FO/LD
DOPLL2
Latch
Selector
fp1
fr1
fr2
fp2
128/129
(4)
(7)
(1)
(20)
(2)
(3)
(18)
(10)
(19)
(17)
(14)
(5)
(6)
(8)
(13)
(11)
(16)
(15)
(12)
OSC_OUT
(9)
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