
Prel i m nary -21- November 1997
W9966CF/TF
Video Camera Interface Controller with Compression
8 Control and Status Registers
The internal control registers of the W9966CF/TF are selected by performing an address write cycle
with data bits 7-5 = 1X0 (X = 0 for read access, X = 1 for write access). The desired register is
selected by the 5-bit index value. All internal registers are 8-bit wide. Table 8.1 shows the control
register map.
TABLE 8.1 CONTROL REGISTER MAP
INDEX
SYMBOL
DESCRIPTION
00H
CR00
Software Reset Control Register
01H
CR01
CCD/DSP Pixel Data Capture Control Register
02H
CR02
Vertical Down-Scaling Control Register
03H
CR03
Horizontal Down-Scaling Control Register
04H
CR04
Capture Window X-Start Low Register
05H
CR05
Capture Window X-Start High Register
06H
CR06
Capture Window Y-Start Low Register
07H
CR07
Capture Window Y-Start High Register
08H
CR08
Capture Window X-End Low Register
09H
CR09
Capture Window X-End High Register
0AH
CR0A
Capture Window Y-End Low Register
0BH
CR0B
Capture Window Y-End High Register
0CH
CR0C
SRAM Type Register
0DH
CR0D
Enhancement Layer Start Address - 0 Register
0EH
CR0E
Enhancement Layer Start Address - 1 Register
0FH
CR0F
Enhancement Layer Start Address - 2 Register
10H
CR10
Enhancement Layer End Address - 0 Register
11H
CR11
Enhancement Layer End Address - 1 Register
12H
CR12
Enhancement Layer End Address - 2 Register
13H
CR13
Video Encoding Engine Control Register
18H
CR18
Serial Bus Control Register
19H
CR19
General I/O Port Direction Control Register
1AH
CR1A
General I/O Port Data Register
Others
Reserved