參數(shù)資料
型號(hào): W986432DH-5
英文描述: SDRAM|4X512KX32|CMOS|TSSOP|86PIN|PLASTIC
中文描述: 內(nèi)存| 4X512KX32 |的CMOS | TSSOP封裝| 86PIN |塑料
文件頁(yè)數(shù): 23/48頁(yè)
文件大?。?/td> 1283K
代理商: W986432DH-5
W986432DH
Publication Release Date: September 4, 2001
- 23 -
Revision A3
Timing Waveforms, continued
Mode Register Set Cycle
A0
A1
A2
A3
A4
A5
A6
Burst Length
Addressing Mode
CAS Latency
(Test Mode)
A8
Reserved
A0
A7
A0
A9
A0
Write Mode
A10
BS0
A0
A11
A0
BS1
"0"
"0"
A0
A3
A0
A0
1
A0
A0
A0
Addressing Mode
Sequential
Interleave
A0
A9
A0
A0
1
Single Write Mode
A0
Burst read and Burst write
A0
Burst read and single write
A0
A0
A0
A0
A0
A0
A0
A0
A0
A2 A1 A0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
A0
Burst Length
A0
1
2
A0
4
A0
8
Sequential
A0
A0
A0
A0
A0
Interleave
A0
Reserved
A0
Reserved
A0
Full Page
A0
A0
A0
2
A0
3
CAS Latency
Reserved
Reserved
Reserved
A0
A0
A0
A6 A5 A4
0 0 0
0 0 1
A0
A0
A0
0 1 0
0 1 1
1 0 0
t
RSC
t
CMS
t
CMH
t
CMS
t
CMH
t
CMS
t
CMH
t
CMS
t
CMH
t
AS
t
AH
CLK
CS
RAS
CAS
WE
A0-A10
BS0,1
Register
set data
next
command
ReA0
"0"
"0"
"0"
"0"
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