
W981204AH
8M x 4 Banks x 4 bits SDRAM
Revision 1.0 Publication Release Date: June, 2000
- 9 -
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 1 shows the truth
table for the operation commands.
Table 1 Truth Table ( note (1) , (2) )
command
Bank Active
Device state
CKEn-1
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
H
L
L
L
H
H
CKEn
x
x
x
x
x
x
x
x
x
x
x
H
L
H
H
L
L
L
H
H
H
x
x
DQM
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
L
H
BS0,1
v
v
x
v
v
v
v
v
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
A10
v
L
H
L
H
L
H
v
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
A11,
A9-0
v
x
x
v
v
v
v
v
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
CS
L
L
L
L
L
L
L
L
L
L
H
L
L
H
L
x
H
L
x
H
L
x
x
RA
L
L
L
H
H
H
H
L
H
H
x
L
L
x
H
x
x
H
x
x
H
x
x
CAS
H
H
H
L
L
L
L
L
H
H
x
L
L
x
H
x
x
H
x
x
H
x
x
WE
H
L
L
L
L
H
H
L
H
L
x
H
H
x
x
x
x
x
x
x
x
x
x
Idle
Bank Precharge
Any
Precharge All
Any
Write
Active (3)
Write with Autoprecharge
Active (3)
Read
Active (3)
Read with Autoprecharge
Active (3)
Mode Register Set
Idle
No - Operation
Any
Burst Stop
Active (4)
Device Deselect
Any
Auto - Refresh
Idle
Self - Refresh Entry
Idle
Self Refresh Exit
idle
(S.R.)
Clock suspend Mode Entry
Active
Power Down Mode Entry
Idle
Active (5)
Clock Suspend Mode Exit
Active
Power Down Mode Exit
Any
(power down)
Data write/Output Enable
Active
Data Write/Output Disable
Active
Notes: (1) v= valid x = Don't care L= Low Level H= High Level
(2) CKEn signal is input level when commands are provided.
CKEn-1 signal is the input level one clock cycle before the command is issued.
(3) These are state of bank designated by BS0, BS1 signals.
(4) Device state is full page burst operation.
(5) Power Down Mode can not be entered in the burst cycle.
When this command asserts in the burst cycle, device state is clock suspend mode.