參數(shù)資料
型號： W9464G2IB-4
廠商： WINBOND ELECTRONICS CORP
元件分類： DRAM
英文描述： 512K X 32 DDR DRAM, 0.6 ns, PBGA144
封裝： 12 X 12 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, LFBGA-144
文件頁數(shù)： 1/49頁
文件大小： 886K
代理商： W9464G2IB-4
W9464G2IB
512K
× 4 BANKS × 32 BITS GDDR SDRAM
Publication Release Date: Aug. 06, 2009
- 1 -
Revision A01
Table of Contents-
1. GENERAL DESCRIPTION.................................................................................................................................4
2. FEATURES ........................................................................................................................................................4
3. KEY PARAMETERS...........................................................................................................................................5
4. BALL CONFIGURATION....................................................................................................................................6
5. BALL DESCRIPTION .........................................................................................................................................7
6. BLOCK DIAGRAM..............................................................................................................................................9
7. FUNCTIONAL DESCRIPTION .........................................................................................................................10
7.1
Power Up Sequence...........................................................................................................................10
7.2
Command Function ............................................................................................................................11
7.2.1
Bank Activate Command ......................................................................................................11
7.2.2
Bank Precharge Command ..................................................................................................11
7.2.3
Precharge All Command ......................................................................................................11
7.2.4
Write Command ...................................................................................................................11
7.2.5
Write with Auto-precharge Command ..................................................................................11
7.2.6
Read Command ...................................................................................................................11
7.2.7
Read with Auto-precharge Command ..................................................................................11
7.2.8
Mode Register Set Command ..............................................................................................12
7.2.9
Extended Mode Register Set Command ..............................................................................12
7.2.10
No-Operation Command ......................................................................................................12
7.2.11
Burst Read Stop Command..................................................................................................12
7.2.12
Device Deselect Command ..................................................................................................12
7.2.13
Auto Refresh Command .......................................................................................................12
7.2.14
Self Refresh Entry Command...............................................................................................13
7.2.15
Self Refresh Exit Command .................................................................................................13
7.2.16
Data Write Enable /Disable Command .................................................................................13
7.3
Read Operation ..................................................................................................................................13
7.4
Write Operation ..................................................................................................................................14
7.5
Precharge...........................................................................................................................................14
7.6
Burst Termination ...............................................................................................................................14
7.7
Refresh Operation ..............................................................................................................................14
7.8
Power Down Mode .............................................................................................................................15
7.9
Input Clock Frequency Change during Precharge Power Down Mode...............................................15
7.10
Mode Register Operation ...................................................................................................................15
7.10.1
Burst Length field (A2 to A0) ................................................................................................16
7.10.2
Addressing Mode Select (A3)...............................................................................................16
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